(pspec.microwatt_compat == True))
self.alt_reset = Signal(reset_less=True) # not connected yet (microwatt)
+ if self.microwatt_compat:
+
+ if hasattr(pspec, "microwatt_old"):
+ self.microwatt_old = pspec.microwatt_old
+ else:
+ self.microwatt_old = True # PLEASE DO NOT ALTER THIS
+
+ if hasattr(pspec, "microwatt_debug"):
+ self.microwatt_debug = pspec.microwatt_debug
+ else:
+ self.microwatt_debug = True # set to False when using an FPGA
+
# test is SVP64 is to be enabled
self.svp64_en = hasattr(pspec, "svp64") and (pspec.svp64 == True)
# hack method of keeping an eye on whether branch/trap set the PC
self.state_nia = self.core.regs.rf['state'].w_ports['nia']
self.state_nia.wen.name = 'state_nia_wen'
- # and whether SPR pipeline sets DEC or TB
+ # and whether SPR pipeline sets DEC or TB (fu/spr/main_stage.py)
self.state_spr = self.core.regs.rf['state'].w_ports['state1']
# pulse to synchronize the simulator at instruction end
self.srcmask = Signal(64)
self.dstmask = Signal(64)
- # sigh, the wishbone addresses are not wishbone-compliant in microwatt
+ # sigh, the wishbone addresses are not wishbone-compliant
+ # in old versions of microwatt, tplaten_3d_game is a new one
if self.microwatt_compat:
self.ibus_adr = Signal(32, name='wishbone_insn_out.adr')
self.dbus_adr = Signal(32, name='wishbone_data_out.adr')
if self.dbg_domain != 'sync':
comb += dbgclk.eq(ClockSignal())
+ # if using old version of microwatt
# drop the first 3 bits of the incoming wishbone addresses
- # this can go if using later versions of microwatt (not now)
if self.microwatt_compat:
ibus = self.imem.ibus
dbus = self.core.l0.cmpi.wb_bus()
- comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
- comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
- # microwatt verilator debug purposes
- pi = self.core.l0.cmpi.pi.pi
- comb += self.ldst_req.eq(pi.addr_ok_o)
- comb += self.ldst_addr.eq(pi.addr)
+ if self.microwatt_old:
+ comb += self.ibus_adr.eq(Cat(Const(0, 3), ibus.adr))
+ comb += self.dbus_adr.eq(Cat(Const(0, 3), dbus.adr))
+ else:
+ comb += self.ibus_adr.eq(ibus.adr)
+ comb += self.dbus_adr.eq(dbus.adr)
+ if self.microwatt_debug:
+ # microwatt verilator debug purposes
+ pi = self.core.l0.cmpi.pi.pi
+ comb += self.ldst_req.eq(pi.addr_ok_o)
+ comb += self.ldst_addr.eq(pi.addr)
cur_state = self.cur_state
state_r_dectb = state_rf.r_ports['issue'] # DEC/TB
state_w_dectb = state_rf.w_ports['issue'] # DEC/TB
+
with m.FSM() as fsm:
# initiates read of current DEC
with m.If(core_rst):
m.d.sync += self.cur_state.eq(0)
# and, sigh, set configured values, which are also done in regfile
+ # XXX ??? what the hell is the shift for??
m.d.sync += self.cur_state.pc.eq(self.core.pc_at_reset)
m.d.sync += self.cur_state.msr.eq(self.core.msr_at_reset)
easy understanding) come later.
"""
- def fetch_fsm(self, m, dbg, core, nia, is_svp64_mode,
+ def fetch_fsm(self, m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready):
"""fetch FSM
# allow fetch to not run at startup due to I-Cache reset not
# having time to settle. power-on-reset holds dbg.core_stopped_i
with m.State("PRE_IDLE"):
- with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o):
+ with m.If(~dbg.core_stopped_i & ~dbg.core_stop_o & ~core_rst):
m.next = "IDLE"
# waiting (zzz)
with m.FSM(name="issue_fsm"):
+ with m.State("PRE_IDLE"):
+ with m.If(~dbg.core_stop_o & ~core_rst):
+ m.next = "ISSUE_START"
+
# sync with the "fetch" phase which is reading the instruction
# at this point, there is no instruction running, that
# could inadvertently update the PC.
sync = m.d.sync
dbg = self.dbg
pdecode2 = self.pdecode2
+ cur_state = self.cur_state
# temporaries
core_busy_o = core.n.o_data.busy_o # core is busy
# instruction started: must wait till it finishes
with m.State("INSN_ACTIVE"):
- # note changes to MSR, PC and SVSTATE, and DEC/TB
- # these last two are done together, and passed to the
- # DEC/TB FSM
+ # note changes to MSR, PC and SVSTATE
with m.If(self.state_nia.wen & (1 << StateRegs.SVSTATE)):
sync += self.sv_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.MSR)):
sync += self.msr_changed.eq(1)
with m.If(self.state_nia.wen & (1 << StateRegs.PC)):
sync += self.pc_changed.eq(1)
- with m.If((self.state_spr.wen &
- ((1 << StateRegs.DEC) | (1 << StateRegs.TB))).bool()):
+ # and note changes to DEC/TB, to be passed to DEC/TB FSM
+ with m.If(self.state_spr.wen & (1 << StateRegs.TB)):
+ comb += self.pause_dec_tb.eq(1)
+ # but also zero-out the cur_state DEC so that, on
+ # the next instruction, if it is "enable interrupt"
+ # the delay between the DEC/TB FSM reading and updating
+ # cur_state.dec doesn't trigger a spurious interrupt.
+ # the DEC/TB FSM will read the regfile and update to
+ # the correct value, so having cur_state.dec set to zero
+ # for a while is no big deal.
+ with m.If(self.state_spr.wen & (1 << StateRegs.DEC)):
comb += self.pause_dec_tb.eq(1)
+ sync += cur_state.dec.eq(0) # only needs top bit clear
with m.If(~core_busy_o): # instruction done!
comb += exec_pc_o_valid.eq(1)
with m.If(exec_pc_i_ready):
# Issue is where the VL for-loop # lives. the ready/valid
# signalling is used to communicate between the four.
- self.fetch_fsm(m, dbg, core, nia, is_svp64_mode,
+ self.fetch_fsm(m, dbg, core, core_rst, nia, is_svp64_mode,
fetch_pc_o_ready, fetch_pc_i_valid,
fetch_insn_o_valid, fetch_insn_i_ready)
exec_insn_i_valid, exec_insn_o_ready,
exec_pc_o_valid, exec_pc_i_ready)
- # whatever was done above, over-ride it if core reset is held
+ # whatever was done above, over-ride it if core reset is held.
+ # set NIA to pc_at_reset
with m.If(core_rst):
- sync += nia.eq(0)
+ sync += nia.eq(self.core.pc_at_reset)
return m
projects / soc.git / blobdiff