add slow spr regfile regspec support

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 0ba749970e089fb0e82a9782b31fd33674b70967..9feafaf1f9151f66a0d403df81e675ba254fe1eb 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -162,6 +162,7 @@ class TestIssuer(Elaboratable):
 
 if __name__ == '__main__':
     units = {'alu': 1, 'cr': 1, 'branch': 1, 'trap': 1, 'logical': 1,
+             'spr': 1,
              'shiftrot': 1}
     pspec = TestMemPspec(ldst_ifacetype='bare_wb',
                          imem_ifacetype='bare_wb',