whoops, use MSR.IR for I-Cache fetch!

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index ffb7dc9710a21152e88f7d0c98113b4929b44933..ab414f520d8285a06c0bfe34a84b688afc2aaa5a 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -713,7 +713,7 @@ class FetchFSM(ControlBase):
         # set priv / virt mode on I-Cache, sigh
         if isinstance(self.imem, ICache):
             comb += self.imem.i_in.priv_mode.eq(~msr[MSR.PR])
-            comb += self.imem.i_in.virt_mode.eq(msr[MSR.DR])
+            comb += self.imem.i_in.virt_mode.eq(msr[MSR.IR]) # Instr. Redir (VM)
 
         with m.FSM(name='fetch_fsm'):