arse. PLL test_issuer clk_sel_i accidentally only 1 bit not 2

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 55ca090245d1f4d56a69df64ae233a1770c5b331..d8a3d486e358608c3d5bfaf77e0ba841083e642c 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -1235,7 +1235,7 @@ class TestIssuer(Elaboratable):
         if self.pll_en:
             self.pll_test_o = Signal(reset_less=True)
             self.pll_vco_o = Signal(reset_less=True)
-            self.clk_sel_i = Signal(reset_less=True)
+            self.clk_sel_i = Signal(2, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()