Allow updating the PC and SVSTATE registers while stopped

[soc.git] / src / soc / simple / issuer.py

diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 6ba8b39ddcb3bbb9950d0a1ded49d2ceefeb8c9a..f16eb8b50d7011202ec97e67a71a06739b394312 100644 (file)
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -276,6 +276,15 @@ class TestIssuerInternal(Elaboratable):
                 with m.Else():
                     comb += core.core_stopped_i.eq(1)
                     comb += dbg.core_stopped_i.eq(1)
+                    # while stopped, allow updating the PC and SVSTATE
+                    with m.If(self.pc_i.ok):
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+                        sync += pc_changed.eq(1)
+                    with m.If(self.svstate_i.ok):
+                        comb += new_svstate.eq(self.svstate_i.data)
+                        comb += update_svstate.eq(1)
+                        sync += sv_changed.eq(1)
 
             # go fetch the instruction at the current PC
             # at this point, there is no instruction running, that
@@ -350,6 +359,15 @@ class TestIssuerInternal(Elaboratable):
                 with m.Else():
                     comb += core.core_stopped_i.eq(1)
                     comb += dbg.core_stopped_i.eq(1)
+                    # while stopped, allow updating the PC and SVSTATE
+                    with m.If(self.pc_i.ok):
+                        comb += self.state_w_pc.wen.eq(1 << StateRegs.PC)
+                        comb += self.state_w_pc.data_i.eq(self.pc_i.data)
+                        sync += pc_changed.eq(1)
+                    with m.If(self.svstate_i.ok):
+                        comb += new_svstate.eq(self.svstate_i.data)
+                        comb += update_svstate.eq(1)
+                        sync += sv_changed.eq(1)
 
             # need to decode the instruction again, after updating SRCSTEP
             # in the previous state.