add XLEN to issuer_verilog.py defaults to 64

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 6fead5eedfa48ecc5ee225eddf839b6c1a5f6386..4198ae26ff95a6ce25ec86f8b9c92b3249a77cad 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -59,12 +59,19 @@ if __name__ == '__main__':
     parser.add_argument("--disable-svp64", dest='svp64', action="store_false",
                         help="disable SVP64",
                         default=False)
+    parser.add_argument("--xlen", default=64, type=int,
+                        help="Set register width [default 64]")
     # create a module that's directly compatible as a drop-in replacement
     # in microwatt.v
     parser.add_argument("--microwatt-compat", dest='mwcompat',
                         action="store_true",
                         help="generate microwatt-compatible interface",
                         default=False)
+    # allow overlaps in TestIssuer
+    parser.add_argument("--allow-overlap", dest='allow_overlap',
+                        action="store_true",
+                        help="allow overlap in TestIssuer",
+                        default=False)
 
     args = parser.parse_args()
 
@@ -104,8 +111,10 @@ if __name__ == '__main__':
 
     pspec = TestMemPspec(ldst_ifacetype=ldst_ifacetype,
                          imem_ifacetype=imem_ifacetype,
-                         addr_wid=48,
+                         addr_wid=64,
                          mask_wid=8,
+                         # pipeline and integer register file width
+                         XLEN=args.xlen,
                          # must leave at 64
                          reg_wid=64,
                          # set to 32 for instruction-memory width=32
@@ -122,10 +131,11 @@ if __name__ == '__main__':
                          svp64=args.svp64,      # enable SVP64
                          microwatt_mmu=args.mmu,         # enable MMU
                          microwatt_compat=args.mwcompat, # microwatt compatible
+                         allow_overlap=args.allow_overlap, # allow overlap
                          units=units,
                          msr_reset=msr_reset)
-    if args.mwcompat:
-        pspec.core_domain = 'sync'
+    #if args.mwcompat:
+    #    pspec.core_domain = 'sync'
 
     print("mmu", pspec.__dict__["microwatt_mmu"])
     print("nocore", pspec.__dict__["nocore"])
@@ -136,13 +146,16 @@ if __name__ == '__main__':
     print("use_pll", pspec.__dict__["use_pll"])
     print("debug", pspec.__dict__["debug"])
     print("SVP64", pspec.__dict__["svp64"])
+    print("XLEN", pspec.__dict__["XLEN"])
     print("Microwatt compatibility", pspec.__dict__["microwatt_compat"])
 
     if args.mwcompat:
         dut = TestIssuerInternal(pspec)
+        name = "external_core_top"
     else:
         dut = TestIssuer(pspec)
+        name = "test_issuer"
 
-    vl = verilog.convert(dut, ports=dut.external_ports(), name="test_issuer")
+    vl = verilog.convert(dut, ports=dut.external_ports(), name=name)
     with open(args.output_filename, "w") as f:
         f.write(vl)