sigh have to allow external clocks and reset mess even in microwatt-compat

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index 0ff83d691807799ae2c86d5a69fa06f6e8e1af5b..7eb75f9321833ad01ddeab5b595f8a57e6c2e55d 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -124,8 +124,8 @@ if __name__ == '__main__':
                          microwatt_compat=args.mwcompat, # microwatt compatible
                          units=units,
                          msr_reset=msr_reset)
-    if args.mwcompat:
-        pspec.core_domain = 'sync'
+    #if args.mwcompat:
+    #    pspec.core_domain = 'sync'
 
     print("mmu", pspec.__dict__["microwatt_mmu"])
     print("nocore", pspec.__dict__["nocore"])