remove the gpio peripheral which was previously hard-linked to interrupts

[soc.git] / src / soc / simple / issuer_verilog.py

diff --git a/src/soc/simple/issuer_verilog.py b/src/soc/simple/issuer_verilog.py
index b93d47c2ed3b10d6276ce4c6ab4c98e613dfa193..8cd713f8d1393ad85f4179e078e44f47c8d4a37f 100644 (file)
--- a/src/soc/simple/issuer_verilog.py
+++ b/src/soc/simple/issuer_verilog.py
@@ -28,7 +28,7 @@ if __name__ == '__main__':
                          # set to 32 to make data wishbone bus 32-bit
                          #wb_data_wid=32,
                          xics=True,
-                         gpio=True, # for test purposes
+                         gpio=False, # for test purposes
                          units=units)
 
     dut = TestIssuer(pspec)