update SVSTATE to 64 bit length (fortunately very easy)

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 85afa3092ac599eae6b93362070b1badffd36356..180474e123353ec2f5a3fa20735a65e75fb5c0a0 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -134,7 +134,7 @@ class TestRunner(FHDLTestCase):
         m = Module()
         comb = m.d.comb
         pc_i = Signal(32)
-        svstate_i = Signal(32)
+        svstate_i = Signal(64)
 
         if self.microwatt_mmu:
             ldst_ifacetype = 'test_mmu_cache_wb'