use standard create_pdecode in TestRunner
[soc.git] / src / soc / simple / test / test_runner.py
index 342a7ee0720fca4a6c7d2591556289c049417df8..85afa3092ac599eae6b93362070b1badffd36356 100644 (file)
@@ -169,9 +169,8 @@ class TestRunner(FHDLTestCase):
         l0 = core.l0
         regreduce_en = pspec.regreduce_en == True
 
-        # copy of the decoder for simulator
-        simdec = create_pdecode()
-        simdec2 = PowerDecode2(simdec, regreduce_en=regreduce_en)
+        #simdec = create_pdecode()
+        simdec2 = PowerDecode2(None, regreduce_en=regreduce_en)
         m.submodules.simdec2 = simdec2  # pain in the neck
 
         # run core clock at same rate as test clock