Create a new signal for the Simulator to wait on

[soc.git] / src / soc / simple / test / test_runner.py

diff --git a/src/soc/simple/test/test_runner.py b/src/soc/simple/test/test_runner.py
index 9e06b8c2a4c4f25b55749682b5fc25a6e1d11ccf..957cd080b4c92d6b7e6a7c042b6b49cfba5e7850 100644 (file)
--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -257,8 +257,12 @@ class TestRunner(FHDLTestCase):
                     counter = counter + 1
 
                     # wait until executed
-                    yield from wait_for_busy_hi(core)
-                    yield from wait_for_busy_clear(core)
+                    # wait for insn_done high
+                    while not (yield issuer.insn_done):
+                        yield
+                    # wait for insn_done low
+                    while (yield issuer.insn_done):
+                        yield
 
                     # set up simulated instruction (in simdec2)
                     try: