super().__init__()
self.core = core
+ def get_fpregs(self):
+ self.fpregs = []
+ for i in range(32):
+ self.fpregs.append(0)
+
def get_intregs(self):
self.intregs = []
for i in range(32):
def get_crregs(self):
self.crregs = []
for i in range(8):
- rval = yield self.core.regs.cr.regs[i].reg
+ rval = yield self.core.regs.cr.regs[7-i].reg
self.crregs.append(rval)
log("class hdl cr regs", list(map(hex, self.crregs)))
def get_pc(self):
self.pcl = []
self.state = self.core.regs.state
+ # relies on the state.r_port being permanently held as PC
self.pc = yield self.state.r_ports['cia'].o_data
self.pcl.append(self.pc)
log("class hdl pc", hex(self.pc))
def get_mem(self):
+ self.mem = {}
# get the underlying HDL-simulated memory from the L0CacheBuffer
+ if hasattr(self.core, "icache"):
+ # err temporarily ignore memory
+ return # XXX have to work out how to deal with wb_get
hdlmem = get_l0_mem(self.core.l0)
- self.mem = {}
for i in range(hdlmem.depth):
value = yield hdlmem._array[i] # should not really do this
self.mem[i*8] = value