Add support for extended/indexed ld/st

[soc.git] / src / soc / simulator / internalop_sim.py

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 2f435dc7c9f46c064d03300a02a6b3a85b113868..cf71670d87ca34013eaf5eeaf4f118941475d51f 100644 (file)
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -96,9 +96,13 @@ class InternalOpSimulator:
         addr = self.regfile.read_reg(addr_reg)
         
         imm_ok = yield pdecode2.e.imm_data.ok
+        r2_ok = yield pdecode2.e.read_reg2.ok
         if imm_ok:
             imm = yield pdecode2.e.imm_data.data
             addr += imm
+        elif r2_ok:
+            r2_sel = yield pdecode2.e.read_reg2.data
+            addr += self.regfile.read_reg(r2_sel)
         if internal_op == InternalOp.OP_STORE.value:
             val_reg = yield pdecode2.e.read_reg3.data
             val = self.regfile.read_reg(val_reg)