Add memory loads and stores to simulator

[soc.git] / src / soc / simulator / test_sim.py

diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py
index d26aaf72bc9744dae9a1c6432e06243a15ef9f50..3a5e37b92f1795e885abd82513975527251294ee 100644 (file)
--- a/src/soc/simulator/test_sim.py
+++ b/src/soc/simulator/test_sim.py
@@ -68,6 +68,26 @@ class DecoderTestCase(FHDLTestCase):
         simulator = InternalOpSimulator()
 
         self.run_tst(gen, simulator)
+        simulator.regfile.assert_gprs(
+            {1: 0x1234,
+             2: 0x5678,
+             3: 0x68ac,
+             4: 0x1230})
+
+    def test_ldst(self):
+        lst = ["addi 1, 0, 0x1234",
+               "addi 2, 0, 0x5678",
+               "stw  1, 0(2)",
+               "lwz  3, 0(2)"]
+        gen = InstrList(lst)
+
+        simulator = InternalOpSimulator()
+
+        self.run_tst(gen, simulator)
+        simulator.regfile.assert_gprs(
+            {1: 0x1234,
+             2: 0x5678,
+             3: 0x1234})
 
 
 if __name__ == "__main__":