ps = PinSpec(pinbanks, fixedpins, function_names)
- ps.vss("E", ('N', 0), 0, 0, 1)
- ps.vdd("E", ('N', 1), 0, 0, 1)
- ps.sdram1("", ('N', 2), 0, 0, 30)
- ps.vss("I", ('N', 30), 0, 0, 1)
- ps.vdd("I", ('N', 31), 0, 0, 1)
+ ps.vdd("E", ('S', 0), 0, 0, 1)
+ ps.vss("E", ('S', 1), 0, 0, 1)
+ ps.vdd("I", ('S', 2), 0, 5, 1)
+ ps.vss("I", ('S', 3), 0, 5, 1)
+ ps.sdram1("", ('S', 4), 0, 0, 21)
+ ps.mi2c("", ('S', 26), 0, 0, 2)
+ ps.vss("I", ('S', 28), 0, 6, 1)
+ ps.vdd("I", ('S', 29), 0, 6, 1)
+ ps.vss("E", ('S', 30), 0, 13, 1)
+ ps.vdd("E", ('S', 31), 0, 13, 1)
- ps.vss("E", ('E', 0), 0, 1, 1)
- ps.vdd("E", ('E', 1), 0, 1, 1)
- ps.sdram2("", ('E', 2), 0, 0, 12)
- ps.vss("I", ('E', 14), 0, 1, 1)
- ps.vdd("I", ('E', 15), 0, 1, 1)
- ps.gpio("", ('E', 16), 0, 8, 8)
- ps.jtag("", ('E', 25), 0, 0, 4)
+ ps.vdd("E", ('W', 0), 0, 1, 1)
+ ps.vss("E", ('W', 1), 0, 1, 1)
+ ps.vdd("I", ('W', 2), 0, 7, 1)
+ ps.vss("I", ('W', 3), 0, 7, 1)
+ ps.sdram2("", ('W', 4), 0, 0, 12)
+ ps.sdram1("", ('W', 16), 0, 21, 9)
+ ps.uart("0", ('W', 22), 0)
+ ps.jtag("", ('W', 24), 0, 0, 4)
+ ps.vss("I", ('W', 28), 0, 14, 1)
+ ps.vdd("I", ('W', 29), 0, 14, 1)
+ ps.vss("E", ('W', 30), 0, 8, 1)
+ ps.vdd("E", ('W', 31), 0, 8, 1)
- ps.vss("I", ('S', 0), 0, 2, 1)
- ps.vdd("I", ('S', 1), 0, 2, 1)
- ps.mi2c("", ('S', 2), 0, 0, 2)
- ps.mspi("0", ('S', 8), 0)
- ps.uart("0", ('S', 13), 0)
- ps.gpio("", ('S', 15), 0, 0, 8)
- ps.sys("", ('S', 23), 0, 0, 2) # should be 7, to do all PLL pins
- ps.vss("I", ('S', 30), 0, 3, 1)
- ps.vdd("I", ('S', 31), 0, 3, 1)
+ ps.vss("I", ('E', 0), 0, 2, 1)
+ ps.vdd("I", ('E', 1), 0, 2, 1)
+ ps.vdd("I", ('E', 2), 0, 10, 1)
+ ps.vss("I", ('E', 3), 0, 10, 1)
+ ps.mspi("0", ('E', 4), 0)
+ ps.gpio("", ('E', 9), 0, 0, 16)
+ ps.eint("", ('E', 25), 0, 0, 3)
+ ps.vss("I", ('E', 28), 0, 9, 1)
+ ps.vdd("I", ('E', 29), 0, 9, 1)
+ ps.vss("I", ('E', 30), 0, 3, 1)
+ ps.vdd("I", ('E', 31), 0, 3, 1)
- ps.vss("E", ('W', 0), 0, 2, 1)
- ps.vdd("E", ('W', 1), 0, 2, 1)
- #ps.pwm("", ('W', 2), 0, 0, 2) comment out (litex problem 25mar2021)
- ps.eint("", ('W', 4), 0, 0, 3)
- #ps.mspi("1", ('W', 7), 0) comment out (litex problem 25mar2021)
- #ps.sdmmc("0", ('W', 11), 0) # comment out (litex problem 25mar2021)
- ps.vss("I", ('W', 30), 0, 4, 1)
- ps.vdd("I", ('W', 31), 0, 4, 1)
+ ps.vss("E", ('N', 0), 0, 2, 1)
+ ps.vdd("E", ('N', 1), 0, 2, 1)
+ ps.vdd("I", ('N', 2), 0, 12, 1)
+ ps.vss("I", ('N', 3), 0, 12, 1)
+ #ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
+ #ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
+ #ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
+ ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins
+ ps.vss("I", ('N', 28), 0, 11, 1)
+ ps.vdd("I", ('N', 29), 0, 11, 1)
+ ps.vss("I", ('N', 30), 0, 4, 1)
+ ps.vdd("I", ('N', 31), 0, 4, 1)
#ps.mquadspi("1", ('S', 0), 0)
# SYS
elif name.startswith('sys'):
domain = 'SYS'
- if name == 'sys_clk':
+ if name == 'sys_pllclk':
pad = ["p_"+name, name, name]
elif name == 'sys_rst':
#name = 'p_sys_rst_1'
pad = ['p_' + name, name, name]
# GPIO
elif name.startswith('gpio'):
+ gbank = name[4]
domain = 'GPIO'
i = name[7:]
name = 'gpio_' + i
name2 = 'gpio_%%s(%s)' % i
pad = ['p_' + name, name, name2 % 'o', name2 % 'i', name2 % 'oe']
print ("GPIO pad", name, pad)
+ litex_name = "gpio_%s" % gbank + "_".join(name.split("_")[1:])
# I2C master-only
elif name.startswith('mtwi'):
domain = 'MTWI'
- name = 'i2c' + name[4:]
+ suffix = name[4:]
+ litex_name = 'mtwi' + suffix
+ name = 'i2c' + suffix
if name.startswith('i2c_sda'):
name2 = 'i2c_sda_%s'
pad = ['p_'+name, name, name2 % 'o', name2 % 'i', name2 % 'oe']