rename sys_clk to sys_pllclk - conflict with litex

[pinmux.git] / src / spec / ls180.py

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index 5c0783c09aeb93b669e662b2a389bd0ed5b17427..d0393eabf4bee6d0e4adef28cf92fb49c5d1918b 100644 (file)
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -59,38 +59,54 @@ def pinspec():
 
     ps = PinSpec(pinbanks, fixedpins, function_names)
 
-    ps.vss("E", ('N', 0), 0, 0, 1)
-    ps.vdd("E", ('N', 1), 0, 0, 1)
-    ps.sdram1("", ('N', 2), 0, 0, 30)
-    ps.vss("I", ('N', 30), 0, 0, 1)
-    ps.vdd("I", ('N', 31), 0, 0, 1)
+    ps.vdd("E", ('S', 0), 0, 0, 1)
+    ps.vss("E", ('S', 1), 0, 0, 1)
+    ps.vdd("I", ('S', 2), 0, 5, 1)
+    ps.vss("I", ('S', 3), 0, 5, 1)
+    ps.sdram1("", ('S', 4), 0, 0, 21)
+    ps.mi2c("", ('S', 26), 0, 0, 2)
+    ps.vss("I", ('S', 28), 0, 6, 1)
+    ps.vdd("I", ('S', 29), 0, 6, 1)
+    ps.vss("E", ('S', 30), 0, 13, 1)
+    ps.vdd("E", ('S', 31), 0, 13, 1)
 
-    ps.vss("E", ('E', 0), 0, 1, 1)
-    ps.vdd("E", ('E', 1), 0, 1, 1)
-    ps.sdram2("", ('E', 2), 0, 0, 12)
-    ps.vss("I", ('E', 14), 0, 1, 1)
-    ps.vdd("I", ('E', 15), 0, 1, 1)
-    ps.gpio("", ('E', 16), 0, 8, 8)
-    ps.jtag("", ('E', 25), 0, 0, 4)
+    ps.vdd("E", ('W', 0), 0, 1, 1)
+    ps.vss("E", ('W', 1), 0, 1, 1)
+    ps.vdd("I", ('W', 2), 0, 7, 1)
+    ps.vss("I", ('W', 3), 0, 7, 1)
+    ps.sdram2("", ('W', 4), 0, 0, 12)
+    ps.sdram1("", ('W', 16), 0, 21, 9)
+    ps.uart("0", ('W', 22), 0)
+    ps.jtag("", ('W', 24), 0, 0, 4)
+    ps.vss("I", ('W', 28), 0, 14, 1)
+    ps.vdd("I", ('W', 29), 0, 14, 1)
+    ps.vss("E", ('W', 30), 0, 8, 1)
+    ps.vdd("E", ('W', 31), 0, 8, 1)
 
-    ps.vss("I", ('S', 0), 0, 2, 1)
-    ps.vdd("I", ('S', 1), 0, 2, 1)
-    ps.mi2c("", ('S', 2), 0, 0, 2)
-    ps.mspi("0", ('S', 8), 0)
-    ps.uart("0", ('S', 13), 0)
-    ps.gpio("", ('S', 15), 0, 0, 8)
-    ps.sys("", ('S', 23), 0, 0, 2) # should be 7, to do all PLL pins
-    ps.vss("I", ('S', 30), 0, 3, 1)
-    ps.vdd("I", ('S', 31), 0, 3, 1)
+    ps.vss("I", ('E', 0), 0, 2, 1)
+    ps.vdd("I", ('E', 1), 0, 2, 1)
+    ps.vdd("I", ('E', 2), 0, 10, 1)
+    ps.vss("I", ('E', 3), 0, 10, 1)
+    ps.mspi("0", ('E', 4), 0)
+    ps.gpio("", ('E', 9), 0, 0, 16)
+    ps.eint("", ('E', 25), 0, 0, 3)
+    ps.vss("I", ('E', 28), 0, 9, 1)
+    ps.vdd("I", ('E', 29), 0, 9, 1)
+    ps.vss("I", ('E', 30), 0, 3, 1)
+    ps.vdd("I", ('E', 31), 0, 3, 1)
 
-    ps.vss("E", ('W', 0), 0, 2, 1)
-    ps.vdd("E", ('W', 1), 0, 2, 1)
-    #ps.pwm("", ('W', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
-    ps.eint("", ('W', 4), 0, 0, 3)
-    #ps.mspi("1", ('W', 7), 0)       comment out (litex problem 25mar2021)
-    #ps.sdmmc("0", ('W', 11), 0)     # comment out (litex problem 25mar2021)
-    ps.vss("I", ('W', 30), 0, 4, 1)
-    ps.vdd("I", ('W', 31), 0, 4, 1)
+    ps.vss("E", ('N', 0), 0, 2, 1)
+    ps.vdd("E", ('N', 1), 0, 2, 1)
+    ps.vdd("I", ('N', 2), 0, 12, 1)
+    ps.vss("I", ('N', 3), 0, 12, 1)
+    #ps.pwm("", ('N', 2), 0, 0, 2)  comment out (litex problem 25mar2021)
+    #ps.mspi("1", ('N', 7), 0)       comment out (litex problem 25mar2021)
+    #ps.sdmmc("0", ('N', 11), 0)     # comment out (litex problem 25mar2021)
+    ps.sys("", ('N', 22), 0, 0, 6) # should be 6, to do all PLL pins
+    ps.vss("I", ('N', 28), 0, 11, 1)
+    ps.vdd("I", ('N', 29), 0, 11, 1)
+    ps.vss("I", ('N', 30), 0, 4, 1)
+    ps.vdd("I", ('N', 31), 0, 4, 1)
 
     #ps.mquadspi("1", ('S', 0), 0)
 
@@ -190,7 +206,7 @@ def pinparse(psp, pinspec):
         # SYS
         elif name.startswith('sys'):
             domain = 'SYS'
-            if name == 'sys_clk':
+            if name == 'sys_pllclk':
                 pad = ["p_"+name, name, name]
             elif name == 'sys_rst':
                 #name = 'p_sys_rst_1'