def pinspec():
pinbanks = OrderedDict((
- ('N', (32, 2)),
- ('E', (32, 2)),
- ('S', (32, 2)),
- ('W', (32, 2)),
+ ('N', (32, 4)),
+ ('E', (32, 4)),
+ ('S', (32, 4)),
+ ('W', (32, 4)),
))
fixedpins = {
'CTRL_SYS': [
]}
fixedpins = {}
function_names = {
+ 'RG0': 'Gigabit Ethernet 0',
'PWM': 'PWM (pulse-width modulation)',
'MSPI0': 'SPI Master 1 (general)',
'MSPI1': 'SPI Master 2 (SDCard)',
ps.uart("0", ('S', 26), 0)
ps.mspi("0", ('S', 28), 0)
- ps.gpio("", ('E', 0), 0, 0, 6) # GPIO 0-5
- ps.vss("E", ('E', 6), 0, 4, 1)
- ps.vdd("E", ('E', 7), 0, 4, 1)
- ps.vdd("I", ('E', 8), 0, 4, 1)
- ps.vss("I", ('E', 9), 0, 4, 1)
- ps.gpio("", ('E', 10), 0, 6, 3) # GPIO 6-8
- ps.jtag("", ('E', 13), 0, 0, 4)
- ps.gpio("", ('E', 17), 0, 9, 5) # GPIO 9-13
+ ps.gpio("", ('E', 0), 0, 0, 4) # GPIO 0-3
+ ps.rgmii("1", ('E', 0), 1, 0, 4) # RXD0-3
+ ps.vss("E", ('E', 4), 0, 4, 1)
+ ps.vdd("E", ('E', 5), 0, 4, 1)
+ ps.vdd("I", ('E', 6), 0, 4, 1)
+ ps.vss("I", ('E', 7), 0, 4, 1)
+ ps.gpio("", ('E', 8), 0, 6, 10) # GPIO 4-13
+ ps.rgmii("1", ('E', 8), 1, 4, 10) # more RGMII-2
+ ps.jtag("", ('E', 18), 0, 0, 4)
ps.vss("I", ('E', 22), 0, 5, 1)
ps.vdd("I", ('E', 23), 0, 5, 1)
ps.vss("E", ('E', 24), 0, 5, 1)
ps.vdd("E", ('E', 25), 0, 5, 1)
- ps.gpio("", ('E', 26), 0, 14, 2) # GPIO 14-15
- ps.eint("", ('E', 28), 0, 0, 3)
+ ps.gpio("", ('E', 26), 0, 14, 4) # GPIO 14-17
+ ps.rgmii("1", ('E', 26), 1, 14, 5) # more RGMII-2
+ ps.eint("", ('E', 28), 2, 0, 2)
ps.sys("", ('E', 31), 0, 5, 1) # analog VCO out in right top
- ps.vss("E", ('N', 6), 0, 6, 1)
- ps.vdd("E", ('N', 7), 0, 6, 1)
- ps.vdd("I", ('N', 8), 0, 6, 1)
- ps.vss("I", ('N', 9), 0, 6, 1)
+ ps.gpio("", ('N', 0), 0, 0, 4) # GPIO 0-3
+ ps.rgmii("0", ('N', 0), 1, 0, 4) # RXD0-3
+ ps.vss("E", ('N', 4), 0, 6, 1)
+ ps.vdd("E", ('N', 5), 0, 6, 1)
+ ps.vdd("I", ('N', 6), 0, 6, 1)
+ ps.vss("I", ('N', 7), 0, 6, 1)
+ ps.gpio("", ('N', 0), 0, 4, 14) # GPIO 4-17
+ ps.rgmii("0", ('N', 8), 1, 4, 14) # more RGMII-1
#ps.pwm("", ('N', 2), 0, 0, 2) comment out (litex problem 25mar2021)
#ps.mspi("1", ('N', 7), 0) comment out (litex problem 25mar2021)
#ps.sdmmc("0", ('N', 11), 0) # comment out (litex problem 25mar2021)
ps.sys("", ('N', 27), 0, 0, 5) # all but analog out in top right
- ps.vss("I", ('N', 22), 0, 7, 1)
- ps.vdd("I", ('N', 23), 0, 7, 1)
- ps.vss("E", ('N', 24), 0, 7, 1)
- ps.vdd("E", ('N', 25), 0, 7, 1)
+ ps.vss("I", ('N', 23), 0, 7, 1)
+ ps.vdd("I", ('N', 24), 0, 7, 1)
+ ps.vss("E", ('N', 25), 0, 7, 1)
+ ps.vdd("E", ('N', 26), 0, 7, 1)
#ps.mquadspi("1", ('S', 0), 0)