rename sys_clk to sys_pllclk - conflict with litex

[pinmux.git] / src / spec / pinfunctions.py

diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index 32f0e78c5ad805a43ab607aa676ecdc94fb52e97..d93f82a9769d3b46241621b878ae9c4f6c766445 100644 (file)
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -285,11 +285,11 @@ def vdd(suffix, bank):
     return (RangePin("-"), [], None)
 
 def sys(suffix, bank):
-    return (['CLK-', 'RST-',
-             'PLLCLK-',                    # PLL ref clock input
+    return (['PLLCLK-',                       # incoming clock (to PLL)
              'PLLSELA0-', 'PLLSELA1-',     # PLL divider-selector
              'PLLTESTOUT+',                # divided-output (for testing)
              'PLLVCOUT+',                  # PLL VCO analog out (for testing)
+             'RST-',                       # reset line
              ], [], 'CLK')
 
 # list functions by name here