# Coriolis2 experimentation started
-TODO by Jock http://bugs.libre-riscv.org/show_bug.cgi?id=217#c44
+Jock, a really enthusiastic and clearly skilled and experienced python
+developer, has this to say about coriolis2:
+
+ As a humble Python developer, I understand the unique status and
+ significance of the Coriolis project, nevertheless I cannot help
+ but notice that it has a huge room for improvement. I genuinely hope
+ that my participation in libre-riscv will also help improve Coriolis.
+
+This was the short version, with a much more
+[detailed insight](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-March/005478.html)
+listed here which would do well as a bugreport. However the time it would
+take is quite significant. We do have funding available from NLNet,
+so if there is anyone that would like to take this on, under the supervision
+of Jean-Paul at LIP6.fr, we can look at facilitating that.
+
+One of the key insights that Jock came up with was that the coding style,
+whilst consistent, is something that specifically has to be learned, and,
+as such, being contrary to PEP8 in so many ways, creates an artificially
+high barrier and learning curve.
+
+Even particularly experienced cross-language developers such as
+myself tend to be able to *read* such code, but editing it, when
+commas separating list items are on the beginning of lines, results in
+syntax errors automatically introduced *without thinking* because we
+automatically add them *at the end* because it looks like one is missing.
+
+This is why we insisted on PEP8 in the
+[HDL workflow](http://libre-riscv.org/HDL_workflow) document.
+
+Other than that: coriolis2 is actually extremely exciting to work with.
+Anyone who has done manual PCB layout will know quite how much of a relief
+it is to have auto-routing: this is what coriolis2 has by the bucket-load,
+*as well* as auto-placement. We are looking at half a *million* objects
+(Cells) to place. Without an auto-router / auto-placer this is just a
+flat-out impossible task.
+
+The first step was to
+[learn and adapt coriolis2](http://bugs.libre-riscv.org/show_bug.cgi?id=178)
+which was needed to find out how much work would be involved, as much as
+anything else, in order to be able to accurately assign the fixed budgets
+to the NLNet milestones. Following on from that, when Jock joined,
+we needed to work out a compact way to express the
+[layout of blocks](http://bugs.libre-riscv.org/show_bug.cgi?id=217#c44)
+and he's well on the way to achieving that.
+
+Some of the pictures from coriolis2 are
+[stunning](bugs.libre-riscv.org/attachment.cgi?id=29). This was an
+experimental routing of the IEEE754 FP 64-bit multiplier. It took
+5 minutes to run, and is around 50,000 gates: as big as most silicon
+ASICs that have formerly been done with Coriolis2, and 50% of the
+practical size that can be handed in one go to the auto-place/auto-router.
+
+Other designs using coriolis2 have been of the form where the major "blocks"
+(such as FPMUL, or Register File) are laid-out automatically in a single-level
+hierarchy, followed by full and total manual layout from that point onwawrds,
+in what is termed in the industry as a "Floorplan".
+With around 500,000 gates to do and many blocks being repeated, this approach
+is not viable for us. We therefore need a *two* level or potentially three
+level hierarchy.
+
+[Explaining this](http://bugs.libre-riscv.org/show_bug.cgi?id=178#c146)
+to Jean-Paul was amusing and challenging. Much bashing of heads against
+walls and keyboards was involved. The basic plan: rather than have
+coriolis2 perform an *entire* layout, in a flat and all-or-nothing fashion,
+we need a much more subtle fine-grained approach, where *sub-blocks* are
+laid-out, then *included* at a given level of hierarchy as "pre-done blocks".
+
+Save and repeat.
+
+This apparently had never been done before, and explaining it in words was
+extremely challenging. Through a massive hack (actively editing the underlying
+HDL files temporarily in between tasks) was the only way to illustrate it.
+However once the lightbulb went on, Jean-Paul was able to get coriolis2's
+c++ code into shape extremely rapidly, and this alone has opened up an
+*entire new avenue* of potential for coriolis2 to be used in industry
+for doing much larger ASICs. Which is precisely the kind of thing that
+our NLNet sponsors (and the EU, from the Horizon 2020 Grant) love. hooray.
+Now if only we could actually go to a conference and talk about it.
# POWER ISA decoder and Simulator
wide interface, we can contract SymbioticEDA to *design* a DDR3 PHY for us,
which both we *and the rest of the worldwide Silicon Community can use
without limitation* because we will ask SymbioticEDA to make the design
-libre-licensed, for anyone to use.
+(and layout) libre-licensed, for anyone to use.
USD 250,000 pays for the mask charges that will allow us to do the 40nm
quad-core ASIC that we have on the roadmap for the second chip. USD
projects / crowdsupply.git / blobdiff