re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / veera.mdwn

diff --git a/veera.mdwn b/veera.mdwn
index f10e62e3357c7f40cf883db535f61d23916fb502..8ae18aa011b0021eac078f36cd8122b38287e3e7 100644 (file)
--- a/veera.mdwn
+++ b/veera.mdwn
@@ -8,6 +8,17 @@ Helping Core Hardware developers.
 
 ## Currently working on
 
+### NLNet.2019.10.Formal
+
+* [Bug #838](https://bugs.libre-soc.org/show_bug.cgi?id=838):
+  sync or at least statically check fields.text, power_decoder, trans/svp64, CSVs between each other
+
+* [Bug #839](https://bugs.libre-soc.org/show_bug.cgi?id=839):
+  SVP64 / Extra-V / ZOLC whitepaper
+
+* [Bug #847](https://bugs.libre-soc.org/show_bug.cgi?id=847):
+  dev\-env\-setup script for binutils-gdb for target powerpc64le\-linux\-gnu
+
 ## Currently deffered
 
  - <https://bugs.libre-soc.org/show_bug.cgi?id=602> Low performance bare minimum functionality SIMD emulator required