re-reserve bit in setvl -- needed for extending registers:

[libreriscv.git] / ztrans_proposal.mdwn

diff --git a/ztrans_proposal.mdwn b/ztrans_proposal.mdwn
index bdf535328e9418aa2afe5e7eeea2ee10c81977cc..5c4505555ddff4580519b72de5aa3e60257e9e5a 100644 (file)
--- a/ztrans_proposal.mdwn
+++ b/ztrans_proposal.mdwn
@@ -1,4 +1,4 @@
-**OBSOLETE**
+**OBSOLETE**, superceded by [[openpower/transcendentals]]
 
 # Zftrans - transcendental operations