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(parent: baa1f12) | patch
shuffle CSR offsets around, offset VL and MVL by one
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Oct 2018 22:40:26 +0000 (23:40 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Tue, 16 Oct 2018 22:40:26 +0000 (23:40 +0100)
commit2fc641682d7f4ead08ddd7feb53bd6428283e57e
tree848b3c161e219f1e70e610d7d6acaf1dc31abf7etree
parentbaa1f128f81c50f02f12411a4fb4210f2989f615commit | diff
shuffle CSR offsets around, offset VL and MVL by one

VL and MVL now span from 1 to XLEN rather than 0 to XLEN-1

also making room for M-Mode and S-Mode CSRs
riscv/encoding.h diff | blob | history
riscv/insns/csrrw.h diff | blob | history
riscv/insns/csrrwi.h diff | blob | history
riscv/processor.cc diff | blob | history
Simple-V augmented version of spike