projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: ee7cb72) | patch
[opcodes, sim, xcc] added mffl.d instruction
authorAndrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Wed, 29 Sep 2010 00:17:04 +0000 (17:17 -0700)
committerAndrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Wed, 29 Sep 2010 00:17:04 +0000 (17:17 -0700)
commit68ddbd26c3643ebe13aa34e58d7dad5dbc1ddbd3
treeaa3b83abc16c3c5069e41478021ba00c028bf031tree
parentee7cb7243e6d297051e1f7bc028196b40d470cb3commit | diff
[opcodes, sim, xcc] added mffl.d instruction

...to be used instead of mff.s when doing int -> DP FP moves on a 32-bit cpu
riscv/execute.h diff | blob | history
riscv/insns/mffl_d.h [new file with mode: 0644] blob
Simple-V augmented version of spike