projects / riscv-isa-sim.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: fed0e53) | patch
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
authorYunsup Lee <yunsup@cs.berkeley.edu>
Tue, 5 Apr 2011 07:50:52 +0000 (00:50 -0700)
committerYunsup Lee <yunsup@cs.berkeley.edu>
Tue, 5 Apr 2011 07:50:52 +0000 (00:50 -0700)
commita174f4bfdbc30e97322d902db8a20c9b71ba0c3a
tree7f25c696354bb354ce31e236ae465f48589088c5tree
parentfed0e53ae71379f3d9cbe31998c72b20e60f332ecommit | diff
[opcodes,pk,sim,xcc] fix vector mem instruction format, add vector seg mem instructions
37 files changed:
riscv/execute.h diff | blob | history
riscv/insns/fldseg_v.h [new file with mode: 0644] blob
riscv/insns/fldsegst_v.h [new file with mode: 0644] blob
riscv/insns/flwseg_v.h [new file with mode: 0644] blob
riscv/insns/flwsegst_v.h [new file with mode: 0644] blob
riscv/insns/fmov_su.h [new file with mode: 0644] blob
riscv/insns/fmov_sv.h [new file with mode: 0644] blob
riscv/insns/fmov_us.h [new file with mode: 0644] blob
riscv/insns/fsdseg_v.h [new file with mode: 0644] blob
riscv/insns/fsdsegst_v.h [new file with mode: 0644] blob
riscv/insns/fswseg_v.h [new file with mode: 0644] blob
riscv/insns/fswsegst_v.h [new file with mode: 0644] blob
riscv/insns/lbseg_v.h [new file with mode: 0644] blob
riscv/insns/lbsegst_v.h [new file with mode: 0644] blob
riscv/insns/lbuseg_v.h [new file with mode: 0644] blob
riscv/insns/lbusegst_v.h [new file with mode: 0644] blob
riscv/insns/ldseg_v.h [new file with mode: 0644] blob
riscv/insns/ldsegst_v.h [new file with mode: 0644] blob
riscv/insns/lhseg_v.h [new file with mode: 0644] blob
riscv/insns/lhsegst_v.h [new file with mode: 0644] blob
riscv/insns/lhuseg_v.h [new file with mode: 0644] blob
riscv/insns/lhusegst_v.h [new file with mode: 0644] blob
riscv/insns/lwseg_v.h [new file with mode: 0644] blob
riscv/insns/lwsegst_v.h [new file with mode: 0644] blob
riscv/insns/lwuseg_v.h [new file with mode: 0644] blob
riscv/insns/lwusegst_v.h [new file with mode: 0644] blob
riscv/insns/mov_su.h [new file with mode: 0644] blob
riscv/insns/mov_sv.h [new file with mode: 0644] blob
riscv/insns/mov_us.h [new file with mode: 0644] blob
riscv/insns/sbseg_v.h [new file with mode: 0644] blob
riscv/insns/sbsegst_v.h [new file with mode: 0644] blob
riscv/insns/sdseg_v.h [new file with mode: 0644] blob
riscv/insns/sdsegst_v.h [new file with mode: 0644] blob
riscv/insns/shseg_v.h [new file with mode: 0644] blob
riscv/insns/shsegst_v.h [new file with mode: 0644] blob
riscv/insns/swseg_v.h [new file with mode: 0644] blob
riscv/insns/swsegst_v.h [new file with mode: 0644] blob
Simple-V augmented version of spike