git.libre-soc.org Git - riscv-isa-sim.git/commit

author	Andrew Waterman <andrew@sifive.com>
	Wed, 8 Feb 2017 22:16:08 +0000 (14:16 -0800)
committer	Andrew Waterman <andrew@sifive.com>
	Wed, 8 Feb 2017 22:16:08 +0000 (14:16 -0800)
commit	a30f1583002563aaae6a0e83c43300eaf81e646e
tree	268f03b6d3fb941a15b9398abe84d10f65c49875	tree
parent	daaf28f7296c0a5f5c90fe6646a4f8a73a720af5	commit \| diff

Encode VM type in sptbr, not mstatus

https://github.com/riscv/riscv-isa-manual/issues/4

Also, refactor gdbserver code to not duplicate VM decoding logic.

riscv/encoding.h		diff \| blob \| history
riscv/gdbserver.cc		diff \| blob \| history
riscv/gdbserver.h		diff \| blob \| history
riscv/mmu.cc		diff \| blob \| history
riscv/mmu.h		diff \| blob \| history
riscv/processor.cc		diff \| blob \| history

Simple-V augmented version of spike

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