- clk_freq=clk_freq)
- if fpga == 'sim':
- self.dramcore = dramcore
- else:
- self.dramcore = drs(dramcore)
- self._decoder.add(self.dramcore.bus, addr=dramcore_addr)
-
- # map the DRAM onto Wishbone, XXX use stall but set classic below
- # XXX WHEN ADDING ASYNCBRIDGE IT IS THE **BRIDGE** THAT MUST
- # XXX HAVE THE STALL SIGNAL, AND THE **BRIDGE** THAT MUST HAVE
- # XXX stall=stb&~ack APPLIED
- drambone = gramWishbone(dramcore, features={'stall'})
- if fpga == 'sim':
- self.drambone = drambone
- else:
- self.drambone = drs(drambone)
- # XXX ADD THE ASYNCBRIDGE NOT THE DRAMBONE.BUS, THEN
- # XXX ADD DRAMBONE.BUS TO ASYNCBRIDGE
- self._decoder.add(self.drambone.bus, addr=ddr_addr)
+ #features=features,
+ clk_freq=self.dram_clk_freq)
+ self.dramcore = drs(dramcore)
+
+ # create the wishbone presentation (wishbone to DFI)
+ drambone = gramWishbone(dramcore, features=features)
+ self.drambone = drs(drambone)
+
+ # this is the case where sys_clk === dram_clk. no ASync Bridge
+ # needed, so just let the phy core and wb-dfi be connected
+ # directly to WB decoder. both are running in "sync" domain
+ # (because of the DomainRenamer, above)
+
+ if ddr_pins is not None and dram_clk_freq is None:
+ self.ddrphy_bus = self.ddrphy.bus
+ self.dramcore_bus = self.dramcore.bus
+ self.drambone_bus = self.drambone.bus
+
+ # this covers the case where sys_clk != dram_clk: three separate
+ # ASync Bridges are constructed (!) and the interface that's to
+ # be wired to the WB decoder is the async bus because that's running
+ # in the "sync" domain.
+
+ if ddr_pins is not None and dram_clk_freq is not None:
+ # Set up Wishbone asynchronous bridge
+ pabus = wishbone.Interface(addr_width=self.ddrphy.bus.addr_width,
+ data_width=self.ddrphy.bus.data_width,
+ granularity=self.ddrphy.bus.granularity,
+ features={'stall'})
+ self.ddrphy_bus = pabus
+ self.ddrphy_bus.memory_map = self.ddrphy.bus.memory_map
+
+ pabr = WBAsyncBridge(master_bus=self.ddrphy_bus,
+ slave_bus=self.ddrphy.bus,
+ master_clock_domain=None,
+ slave_clock_domain="dramsync",
+ address_width=self.ddrphy.bus.addr_width,
+ data_width=self.ddrphy.bus.data_width,
+ granularity=self.ddrphy.bus.granularity,
+ master_features={'stall'})
+ self.ddrphy_async_br = pabr
+
+ # Set up Wishbone asynchronous bridge
+ dab = wishbone.Interface(addr_width=self.dramcore.bus.addr_width,
+ data_width=self.dramcore.bus.data_width,
+ granularity=self.dramcore.bus.granularity,
+ features={'stall'})
+ self.dramcore_bus = dab
+ self.dramcore_bus.memory_map = self.dramcore.bus.memory_map
+
+ dac = WBAsyncBridge(master_bus=self.dramcore_bus,
+ slave_bus=self.dramcore.bus,
+ master_clock_domain=None,
+ slave_clock_domain="dramsync",
+ address_width=self.dramcore.bus.addr_width,
+ data_width=self.dramcore.bus.data_width,
+ granularity=self.dramcore.bus.granularity,
+ master_features={'stall'})
+ self.dramcore_async_br = dac
+
+ # Set up Wishbone asynchronous bridge
+ bab = wishbone.Interface(addr_width=self.drambone.bus.addr_width,
+ data_width=self.drambone.bus.data_width,
+ granularity=self.drambone.bus.granularity,
+ features={'stall'})
+ self.drambone_bus = bab
+ self.drambone_bus.memory_map = self.drambone.bus.memory_map
+
+ bab = WBAsyncBridge(master_bus=self.drambone_bus,
+ slave_bus=self.drambone.bus,
+ master_clock_domain=None,
+ slave_clock_domain="dramsync",
+ address_width=self.drambone.bus.addr_width,
+ data_width=self.drambone.bus.data_width,
+ granularity=self.drambone.bus.granularity,
+ master_features={'stall'})
+ self.drambone_async_br = bab
+
+ if ddr_pins is not None:
+ # Add wishbone decoders
+ self._decoder.add(self.dramcore_bus, addr=dramcore_addr)
+ self._decoder.add(self.drambone_bus, addr=ddr_addr)
+ self._decoder.add(self.ddrphy_bus, addr=ddrphy_addr)