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CSR decoding
author
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 26 Nov 2018 02:30:38 +0000
(
02:30
+0000)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Mon, 26 Nov 2018 02:30:38 +0000
(
02:30
+0000)
cpu.py
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diff --git
a/cpu.py
b/cpu.py
index e0a6881c9248769e328e73ed1498ec4cf0bd49e3..b79615c80e5d1ef3571e0a6a6bb77e2ab0e61366 100644
(file)
--- a/
cpu.py
+++ b/
cpu.py
@@
-610,6
+610,19
@@
class CPU(Module):
csr_op_is_valid)
#self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
csr_op_is_valid)
#self.comb += self.handle_trap(m, mstatus, ft, dc, load_store_misaligned)
+ # CSR decoding
+ csr_number = Signal(12)
+ csr_input_value = Signal(32)
+ csr_reads = Signal()
+ csr_writes = Signal()
+
+ self.comb += csr_number.eq(dc.immediate)
+ self.comb += csr_input_value.eq(Mux(dc.funct3[2],
+ dc.rs1,
+ register_rs1))
+ self.comb += csr_reads.eq(dc.funct3[1] | (dc.rd != 0))
+ self.comb += csr_writes.eq(~dc.funct3[1] | (dc.rs1 != 0))
+
if __name__ == "__main__":
example = CPU()
if __name__ == "__main__":
example = CPU()