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last changeThu, 29 Nov 2018 00:25:17 +0000 (00:25 +0000)
shortlog
2018-11-29 Luke Kenneth... add Makefile for verilog compilation master
2018-11-28 Luke Kenneth... add to .gitignore
2018-11-28 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2018-11-28 Jacob Lifshayadd instructions for using iverilog
2018-11-28 Luke Kenneth... handle_trap returns values that get manually transferre...
2018-11-27 Luke Kenneth... remove trap_handled, remove w_en
2018-11-27 Luke Kenneth... experiment with separate cpu handle csr module
2018-11-27 Luke Kenneth... move handle trap out to separate module, bit messy
2018-11-27 Luke Kenneth... split out cpu handle_trap
2018-11-27 Luke Kenneth... split out cpu_mip to separate module
2018-11-27 Luke Kenneth... split out cpu_mie into separate module
2018-11-27 Luke Kenneth... split out MStatus to separate module
2018-11-27 Luke Kenneth... split cpu loadstore calc out
2018-11-26 Luke Kenneth... break out cpu load/store calculation into separate...
2018-11-26 Luke Kenneth... move get_fetch_action to separate verilog file
2018-11-26 Luke Kenneth... prepare get_fetch_action for move to separate module
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heads
11 months ago master