remove trap_handled, remove w_en

diff --git a/cpu.py b/cpu.py
index fac67d4435b93c473e6bf349aafe228ad238b2dc..b12f90e8558223e9274b8b9f9567f6569b601e0b 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -269,7 +269,6 @@ class CPU(Module):
         # fetch action ack trap
         i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
                 [self.handle_trap.eq(1),
-                 self.regs.w_en.eq(0) # no writing to registers
                 ]
               )
 
@@ -304,7 +303,6 @@ class CPU(Module):
         i = i.Elif((dc.act & (DA.fence | DA.fence_i |
                               DA.store | DA.branch)) != 0,
                 # do nothing
-               self.regs.w_en.eq(0) # no writing to registers
               )
 
         return i

diff --git a/cpu_handle_trap.py b/cpu_handle_trap.py
index eaf3dafc441b9950d768a08bc9bf29fe2091eb28..c77be862b9893f5022ea87c2ddca9456495a9fdf 100644 (file)
--- a/cpu_handle_trap.py
+++ b/cpu_handle_trap.py
@@ -45,7 +45,6 @@ class CPUHandleTrap(Module):
         self.reset = ResetSignal()
 
         self.handle_trap = Signal()
-        self.trap_handled = Signal()
         self.ft_action = Signal(fetch_action)
         self.dc_action = Signal(decode_action)
         self.dc_immediate = Signal(32)
@@ -102,11 +101,7 @@ class CPUHandleTrap(Module):
 
         s.append(i)
 
-        self.sync += If(self.handle_trap,
-                        [s, self.trap_handled.eq(1)]
-                     ).Else(
-                        self.trap_handled.eq(0)
-                     )
+        self.sync += If(self.handle_trap, s)
 
 
 if __name__ == "__main__":
@@ -114,7 +109,6 @@ if __name__ == "__main__":
     print(verilog.convert(example,
          {
             example.handle_trap,
-            example.trap_handled,
             example.ft_action,
             example.dc_immediate,
             example.mcause,