rv32.git
12 months agoadd Makefile for verilog compilation master
Luke Kenneth Casson Leighton [Thu, 29 Nov 2018 00:25:17 +0000 (00:25 +0000)]
add Makefile for verilog compilation

12 months agoadd to .gitignore
Luke Kenneth Casson Leighton [Wed, 28 Nov 2018 08:36:31 +0000 (08:36 +0000)]
add to .gitignore

12 months agoMerge branch 'master' of ssh://git.libre-riscv.org:922/rv32
Jacob Lifshay [Wed, 28 Nov 2018 07:57:25 +0000 (23:57 -0800)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/rv32

12 months agoadd instructions for using iverilog
Jacob Lifshay [Wed, 28 Nov 2018 07:54:15 +0000 (23:54 -0800)]
add instructions for using iverilog

12 months agohandle_trap returns values that get manually transferred on trap
Luke Kenneth Casson Leighton [Wed, 28 Nov 2018 03:34:22 +0000 (03:34 +0000)]
handle_trap returns values that get manually transferred on trap

12 months agoremove trap_handled, remove w_en
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 08:57:26 +0000 (08:57 +0000)]
remove trap_handled, remove w_en

12 months agoexperiment with separate cpu handle csr module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 08:55:10 +0000 (08:55 +0000)]
experiment with separate cpu handle csr module

12 months agomove handle trap out to separate module, bit messy
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 04:28:28 +0000 (04:28 +0000)]
move handle trap out to separate module, bit messy

12 months agosplit out cpu handle_trap
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 04:08:38 +0000 (04:08 +0000)]
split out cpu handle_trap

12 months agosplit out cpu_mip to separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:40:34 +0000 (02:40 +0000)]
split out cpu_mip to separate module

12 months agosplit out cpu_mie into separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:29:12 +0000 (02:29 +0000)]
split out cpu_mie into separate module

12 months agosplit out MStatus to separate module
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 02:14:16 +0000 (02:14 +0000)]
split out MStatus to separate module

12 months agosplit cpu loadstore calc out
Luke Kenneth Casson Leighton [Tue, 27 Nov 2018 00:20:06 +0000 (00:20 +0000)]
split cpu loadstore calc out

12 months agobreak out cpu load/store calculation into separate module
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 23:58:55 +0000 (23:58 +0000)]
break out cpu load/store calculation into separate module

12 months agomove get_fetch_action to separate verilog file
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 12:33:35 +0000 (12:33 +0000)]
move get_fetch_action to separate verilog file

12 months agoprepare get_fetch_action for move to separate module
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 11:19:14 +0000 (11:19 +0000)]
prepare get_fetch_action for move to separate module

12 months agowhoops missed out branch_taken logic from fetch_action
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 11:12:54 +0000 (11:12 +0000)]
whoops missed out branch_taken logic from fetch_action

12 months agorename register varnames to regfile
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 09:38:51 +0000 (09:38 +0000)]
rename register varnames to regfile

12 months agoreorganise cpu regfile, to separate module, with 2R1W interface
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 09:35:25 +0000 (09:35 +0000)]
reorganise cpu regfile, to separate module, with 2R1W interface

12 months agocomplete csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 07:41:29 +0000 (07:41 +0000)]
complete csrs

12 months agoadd misa and mstatus csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 06:26:40 +0000 (06:26 +0000)]
add misa and mstatus csrs

12 months agoadd clock domains doc to README
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 05:44:42 +0000 (05:44 +0000)]
add clock domains doc to README

12 months agostart adding csrs
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:50:26 +0000 (04:50 +0000)]
start adding csrs

12 months agomove stuff to MInfo
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:45:05 +0000 (04:45 +0000)]
move stuff to MInfo

12 months agosplit CSR to separate class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:21:55 +0000 (04:21 +0000)]
split CSR to separate class

12 months agoadd handle_main
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 04:10:18 +0000 (04:10 +0000)]
add handle_main

12 months agoadd counters (TODO)
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 03:00:17 +0000 (03:00 +0000)]
add counters (TODO)

12 months agoadd csr_is_valid
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:54:25 +0000 (02:54 +0000)]
add csr_is_valid

12 months agostart on csr op valid
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:34:51 +0000 (02:34 +0000)]
start on csr op valid

12 months agoCSR decoding
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:30:38 +0000 (02:30 +0000)]
CSR decoding

12 months agoadd handle_trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:24:46 +0000 (02:24 +0000)]
add handle_trap

12 months agoadd handle_trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 02:19:23 +0000 (02:19 +0000)]
add handle_trap

12 months agoadd handle trap
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:37:58 +0000 (01:37 +0000)]
add handle trap

12 months agocomplete get_fetch_action, move to class Fetch
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:21:03 +0000 (01:21 +0000)]
complete get_fetch_action, move to class Fetch

12 months agostart converting get_fetch_action
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 01:01:03 +0000 (01:01 +0000)]
start converting get_fetch_action

12 months agofetch output state class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:50:59 +0000 (00:50 +0000)]
fetch output state class

12 months agocreate Fetch class
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:48:34 +0000 (00:48 +0000)]
create Fetch class

12 months agoadd get_fetch_action ready for conversion
Luke Kenneth Casson Leighton [Mon, 26 Nov 2018 00:41:06 +0000 (00:41 +0000)]
add get_fetch_action ready for conversion

12 months agoadd to README
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 23:54:06 +0000 (23:54 +0000)]
add to README

12 months agoclass-ify fetch_action
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 11:16:16 +0000 (11:16 +0000)]
class-ify fetch_action

12 months agoadd mstatus, mip and vendor/arch/mimpl
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 11:07:19 +0000 (11:07 +0000)]
add mstatus, mip and vendor/arch/mimpl

12 months agoadd MISA and MIE
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 10:20:49 +0000 (10:20 +0000)]
add MISA and MIE

12 months agoadd more logic and mstatus
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 08:17:02 +0000 (08:17 +0000)]
add more logic and mstatus

12 months agocalculate lui_auipc
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:43:31 +0000 (06:43 +0000)]
calculate lui_auipc

12 months agominor reorg, add alu
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:23:36 +0000 (06:23 +0000)]
minor reorg, add alu

12 months agominor reorg, add alu
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 06:21:00 +0000 (06:21 +0000)]
minor reorg, add alu

12 months agoconvert loaded value
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 05:42:46 +0000 (05:42 +0000)]
convert loaded value

12 months agoload value
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 04:31:19 +0000 (04:31 +0000)]
load value

12 months agomore cpu logic
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 03:15:58 +0000 (03:15 +0000)]
more cpu logic

12 months agosmall cpu reorg
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 02:18:20 +0000 (02:18 +0000)]
small cpu reorg

12 months agoadd load/store misaligned
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 01:56:05 +0000 (01:56 +0000)]
add load/store misaligned

12 months agoadd CPU decoder instance
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 01:15:43 +0000 (01:15 +0000)]
add CPU decoder instance

12 months agoadd cpuFetchStage instance
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 00:56:47 +0000 (00:56 +0000)]
add cpuFetchStage instance

12 months agoadding call out to cpu_memory_interface verilog module in cpu.py
Luke Kenneth Casson Leighton [Sun, 25 Nov 2018 00:11:10 +0000 (00:11 +0000)]
adding call out to cpu_memory_interface verilog module in cpu.py

12 months agostub cpu.py
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 12:15:46 +0000 (12:15 +0000)]
stub cpu.py

12 months agotidyup
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:37:16 +0000 (01:37 +0000)]
tidyup

12 months agodocument decode functions
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:36:42 +0000 (01:36 +0000)]
document decode functions

12 months agotidyup
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:34:30 +0000 (01:34 +0000)]
tidyup

12 months agono immediate constant, make 32-bit wide
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:22:06 +0000 (01:22 +0000)]
no immediate constant, make 32-bit wide

12 months agobig reorg, class-ify constants
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:20:35 +0000 (01:20 +0000)]
big reorg, class-ify constants

12 months agobig reorg, class-ify constants
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 01:19:23 +0000 (01:19 +0000)]
big reorg, class-ify constants

12 months agocleanup cpu_decode.py
Luke Kenneth Casson Leighton [Sat, 24 Nov 2018 00:01:26 +0000 (00:01 +0000)]
cleanup cpu_decode.py

12 months agomore cpu decode conversion
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 23:44:51 +0000 (23:44 +0000)]
more cpu decode conversion

12 months agoadd cpu decode cases
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 15:23:49 +0000 (15:23 +0000)]
add cpu decode cases

12 months agoadd cpu_decoder.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 12:21:52 +0000 (12:21 +0000)]
add cpu_decoder.py

12 months agoadd riscvdefs.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 11:36:50 +0000 (11:36 +0000)]
add riscvdefs.py

12 months agoremove sync set output_state
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 10:31:26 +0000 (10:31 +0000)]
remove sync set output_state

12 months agosort out memory_interface_fetch_address
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 07:55:23 +0000 (07:55 +0000)]
sort out memory_interface_fetch_address

12 months agoadd some arbitrary math into example
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:56:49 +0000 (03:56 +0000)]
add some arbitrary math into example

12 months agocall value_bits_sign direct
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:52:20 +0000 (03:52 +0000)]
call value_bits_sign direct

12 months agocan`t stand list incomprehension
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:45:44 +0000 (03:45 +0000)]
can`t stand list incomprehension

12 months agoadd example pipeline.py
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 03:44:24 +0000 (03:44 +0000)]
add example pipeline.py

12 months agocorrections, clash fetch_action and self.fetch_action
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:08:15 +0000 (00:08 +0000)]
corrections, clash fetch_action and self.fetch_action

12 months agoadd conversion code, see what happens
Luke Kenneth Casson Leighton [Fri, 23 Nov 2018 00:01:27 +0000 (00:01 +0000)]
add conversion code, see what happens

12 months agomore cleanup
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 22:35:59 +0000 (22:35 +0000)]
more cleanup

12 months agocleanup, use sync instead of comb where appropriate
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 19:12:39 +0000 (19:12 +0000)]
cleanup, use sync instead of comb where appropriate

12 months agoadd cpudefs.py
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 02:02:56 +0000 (02:02 +0000)]
add cpudefs.py

12 months agoreorg case statement
Luke Kenneth Casson Leighton [Thu, 22 Nov 2018 00:21:59 +0000 (00:21 +0000)]
reorg case statement

12 months agoconvert case statement
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 15:11:28 +0000 (15:11 +0000)]
convert case statement

12 months agoconverting cpu_fetch_stage to migen
Luke Kenneth Casson Leighton [Wed, 21 Nov 2018 14:38:42 +0000 (14:38 +0000)]
converting cpu_fetch_stage to migen

20 months agoadd licenses and readme
Jacob Lifshay [Wed, 21 Mar 2018 01:19:21 +0000 (18:19 -0700)]
add licenses and readme