convert loaded value

diff --git a/cpu.py b/cpu.py
index efe7270a937ece24e5642f6dcda05526410f5c6d..07ba97316f588a10d3291bb7d65dfe8af91876a2 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -228,6 +228,22 @@ class CPU(Module):
 
         self.comb += unmasked_loaded_value.eq(Cat(b0, b1, b23))
 
+        # XXX not obvious
+        loaded_value = Signal(32)
+
+        b0 = unmasked_loaded_value[0:8]
+        b1 = Mux(decoder_funct3[0:2] == 0,
+                Replicate(~decoder_funct3[2] & unmasked_loaded_value[7], 8),
+                unmasked_loaded_value[8:16])
+        b2 = Mux(decoder_funct3[1] == 0,
+                Replicate(~decoder_funct3[2] &
+                           Mux(decoder_funct3[0], unmasked_loaded_value[15],
+                                                  unmasked_loaded_value[7]),
+                          16),
+                unmasked_loaded_value[16:32])
+
+        self.comb += loaded_value.eq(Cat(b0, b1, b2))
+
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,
@@ -243,12 +259,6 @@ if __name__ == "__main__":
 
 """
 
-    wire [31:0] loaded_value;
-
-    assign loaded_value[7:0] = unmasked_loaded_value[7:0];
-    assign loaded_value[15:8] = decoder_funct3[1:0] == 0 ? ({8{~decoder_funct3[2] & unmasked_loaded_value[7]}}) : unmasked_loaded_value[15:8];
-    assign loaded_value[31:16] = decoder_funct3[1] == 0 ? ({16{~decoder_funct3[2] & (decoder_funct3[0] ? unmasked_loaded_value[15] : unmasked_loaded_value[7])}}) : unmasked_loaded_value[31:16];
-
     assign memory_interface_rw_active = ~reset
                                         & (fetch_output_state == `fetch_output_state_valid)
                                         & ~load_store_misaligned