class JTAG(DMITAP, Pins):
# 32-bit data width here so that it matches with litex
class JTAG(DMITAP, Pins):
# 32-bit data width here so that it matches with litex
DMITAP.__init__(self, ir_width=4)
Pins.__init__(self, pinset)
DMITAP.__init__(self, ir_width=4)
Pins.__init__(self, pinset)
# create and connect wishbone
self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
address_width=30, data_width=wb_data_wid,
granularity=8, # 8-bit wide
# create and connect wishbone
self.wb = self.add_wishbone(ircodes=[5, 6, 7], features={'err'},
address_width=30, data_width=wb_data_wid,
granularity=8, # 8-bit wide
# use this for enable/disable of parts of the ASIC.
# XXX make sure to add the _en sig to en_sigs list
# use this for enable/disable of parts of the ASIC.
# XXX make sure to add the _en sig to en_sigs list
self.wb_sram_en = Signal(reset=1)
self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
self.wb_sram_en)
self.wb_sram_en = Signal(reset=1)
self.en_sigs = en_sigs = Cat(self.wb_icache_en, self.wb_dcache_en,
self.wb_sram_en)
def elaborate(self, platform):
m = super().elaborate(platform)
def elaborate(self, platform):
m = super().elaborate(platform)