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ShiftRegInit: use the rocket-chip version since it is there now
author
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 00:51:40 +0000
(17:51 -0700)
committer
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 00:51:40 +0000
(17:51 -0700)
src/main/scala/devices/i2c/I2CPins.scala
patch
|
blob
|
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src/main/scala/devices/mockaon/MockAONPeriphery.scala
patch
|
blob
|
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src/main/scala/devices/spi/SPIPhysical.scala
patch
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src/main/scala/devices/uart/UARTPeriphery.scala
patch
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diff --git
a/src/main/scala/devices/i2c/I2CPins.scala
b/src/main/scala/devices/i2c/I2CPins.scala
index bae0bc6b435a1c1ad781ff3b39486fd708b80362..1a02a59a72728ba6d518187e5dbcdc9c815735de 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPins.scala
+++ b/
src/main/scala/devices/i2c/I2CPins.scala
@@
-3,9
+3,8
@@
package sifive.blocks.devices.i2c
import Chisel._
import chisel3.experimental.{withClockAndReset}
import Chisel._
import chisel3.experimental.{withClockAndReset}
+import freechips.rocketchip.util.ShiftRegInit
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
-import sifive.blocks.util.ShiftRegisterInit
-
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@@
-19,11
+18,11
@@
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
- i2c.scl.in := ShiftReg
isterInit(scl.i.ival, syncStages,
Bool(true))
+ i2c.scl.in := ShiftReg
Init(scl.i.ival, syncStages, init =
Bool(true))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
- i2c.sda.in := ShiftReg
isterInit(sda.i.ival, syncStages,
Bool(true))
+ i2c.sda.in := ShiftReg
Init(sda.i.ival, syncStages, init =
Bool(true))
}
}
}
}
}
}
diff --git
a/src/main/scala/devices/mockaon/MockAONPeriphery.scala
b/src/main/scala/devices/mockaon/MockAONPeriphery.scala
index 3f0d3268b3485c7c0deb80e9ac9869b9f14ddb9b..b20bee24e35cc3abc6b2a676ace53ca6dde3f590 100644
(file)
--- a/
src/main/scala/devices/mockaon/MockAONPeriphery.scala
+++ b/
src/main/scala/devices/mockaon/MockAONPeriphery.scala
@@
-3,6
+3,7
@@
package sifive.blocks.devices.mockaon
import Chisel._
import freechips.rocketchip.config.Field
import Chisel._
import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
@@
-43,7
+44,7
@@
trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
outer.aon.module.reset := Bool(true)
// Synchronize the external toggle into the clint
outer.aon.module.reset := Bool(true)
// Synchronize the external toggle into the clint
- val rtc_sync = S
hiftRegister(outer.aon.module.io.rtc.asUInt.toBool, 3
)
+ val rtc_sync = S
ynchronizerShiftReg(outer.aon.module.io.rtc.asUInt.toBool, 3, Some("rtc")
)
val rtc_last = Reg(init = Bool(false), next=rtc_sync)
val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
val rtc_last = Reg(init = Bool(false), next=rtc_sync)
val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
diff --git
a/src/main/scala/devices/spi/SPIPhysical.scala
b/src/main/scala/devices/spi/SPIPhysical.scala
index a9ce0760ce30a793c29522d47d99d4a3db4811b6..25ad882681e73e42b09a10b7f8a117a942dcce35 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPhysical.scala
+++ b/
src/main/scala/devices/spi/SPIPhysical.scala
@@
-2,7
+2,7
@@
package sifive.blocks.devices.spi
import Chisel._
package sifive.blocks.devices.spi
import Chisel._
-import
sifive.blocks.util.ShiftRegister
Init
+import
freechipchips.rocketchip.util.ShiftReg
Init
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
@@
-39,8
+39,8
@@
class SPIPhysical(c: SPIParamsBase) extends Module {
val last = Wire(init = Bool(false))
// Delayed versions
val setup_d = Reg(next = setup)
val last = Wire(init = Bool(false))
// Delayed versions
val setup_d = Reg(next = setup)
- val sample_d = ShiftReg
isterInit(sample, c.sampleDelay,
Bool(false))
- val last_d = ShiftReg
isterInit(last, c.sampleDelay,
Bool(false))
+ val sample_d = ShiftReg
Init(sample, c.sampleDelay, init =
Bool(false))
+ val last_d = ShiftReg
Init(last, c.sampleDelay, init =
Bool(false))
val scnt = Reg(init = UInt(0, c.countBits))
val tcnt = Reg(io.ctrl.sck.div)
val scnt = Reg(init = UInt(0, c.countBits))
val tcnt = Reg(io.ctrl.sck.div)
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index 00e5fdd856e5003fda3062050b8fe172a07d85f0..4a517cb306c7a1db099e1b71e4e7c98c800ecc1a 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-4,10
+4,10
@@
package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
+import freechips.rocketchip.util.ShiftRegInit
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
-import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
case object PeripheryUARTKey extends Field[Seq[UARTParams]]
@@
-51,7
+51,7
@@
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
- uart.rxd := ShiftReg
isterInit(rxd_t, syncStages,
Bool(true))
+ uart.rxd := ShiftReg
Init(rxd_t, n = syncStages, init =
Bool(true))
}
}
}
}
}
}