src/main/scala/devices/mockaon/MockAONPeriphery.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.mockaon
   3
   4 import Chisel._
   5 import freechips.rocketchip.config.Field
   6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
   7 import freechips.rocketchip.devices.debug.HasPeripheryDebug
   8 import freechips.rocketchip.devices.tilelink.HasPeripheryClint
   9 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
  10 import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
  11 import freechips.rocketchip.util.ResetCatchAndSync
  12
  13 case object PeripheryMockAONKey extends Field[MockAONParams]
  14
  15 trait HasPeripheryMockAON extends HasPeripheryBus
  16     with HasInterruptBus
  17     with HasPeripheryClint
  18     with HasPeripheryDebug {
  19   // We override the clock & Reset here so that all synchronizers, etc
  20   // are in the proper clock domain.
  21   val mockAONParams= p(PeripheryMockAONKey)
  22   val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
  23   aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
  24   ibus.fromAsync := aon.intnode
  25 }
  26
  27 trait HasPeripheryMockAONBundle {
  28   val aon: MockAONWrapperBundle
  29   def coreResetCatchAndSync(core_clock: Clock) = {
  30     ResetCatchAndSync(core_clock, aon.rsts.corerst, 20)
  31   }
  32 }
  33
  34 trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripheryMockAONBundle {
  35   val outer: HasPeripheryMockAON
  36   val aon = IO(new MockAONWrapperBundle)
  37
  38   aon <> outer.aon.module.io
  39
  40   // Explicit clock & reset are unused in MockAONWrapper.
  41   // Tie  to check this assumption.
  42   outer.aon.module.clock := Bool(false).asClock
  43   outer.aon.module.reset := Bool(true)
  44
  45   // Synchronize the external toggle into the clint
  46   val rtc_sync = ShiftRegister(outer.aon.module.io.rtc.asUInt.toBool, 3)
  47   val rtc_last = Reg(init = Bool(false), next=rtc_sync)
  48   val rtc_tick = Reg(init = Bool(false), next=(rtc_sync & (~rtc_last)))
  49
  50   outer.clint.module.io.rtcTick := rtc_tick
  51
  52   outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
  53 }