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Implement a debug port on the pseudo 1W/1R SRAM
authorCesar Strauss <cestrauss@gmail.com>
Sun, 3 Apr 2022 18:50:43 +0000 (15:50 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sun, 3 Apr 2022 18:50:43 +0000 (15:50 -0300)
Exposes the debug ports of the underlying memories.
This is needed to assist the induction proof.


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