[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec insts

diff --git a/riscv/execute.h b/riscv/execute.h
index b258957e62b43116e7e280ccc5e9659755b0b1a2..6ea79c8d99bb2d7d17199ecc3e4a75cc8e03db40 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -113,359 +113,319 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0xb:
   {
-        if((insn.bits & 0x1ffff) == 0x230b)
+        if((insn.bits & 0x1ffff) == 0x128b)
         {
-          #include "insns/lwuseg_v.h"
+          #include "insns/vlsthu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x10b)
+        if((insn.bits & 0xfff) == 0xb0b)
         {
-          #include "insns/lw_v.h"
+          #include "insns/vlsegstwu.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x30b)
         {
-          #include "insns/lwu_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x1810b)
-        {
-          #include "insns/fmov_su.h"
+          #include "insns/vlwu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x290b)
-        {
-          #include "insns/swseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x280b)
+        if((insn.bits & 0x3fffff) == 0x8b)
         {
-          #include "insns/sbseg_v.h"
+          #include "insns/vlh.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x20b)
+        if((insn.bits & 0x1ffff) == 0x158b)
         {
-          #include "insns/lbu_v.h"
+          #include "insns/vflstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x100b)
+        if((insn.bits & 0x3fffff) == 0xb)
         {
-          #include "insns/lbst_v.h"
+          #include "insns/vlb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x218b)
+        if((insn.bits & 0x3fffff) == 0x18b)
         {
-          #include "insns/ldseg_v.h"
+          #include "insns/vld.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x180b)
+        if((insn.bits & 0x1ffff) == 0x150b)
         {
-          #include "insns/sbst_v.h"
+          #include "insns/vflstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x58b)
+        if((insn.bits & 0x3fffff) == 0x10b)
         {
-          #include "insns/fld_v.h"
+          #include "insns/vlw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x208b)
+        if((insn.bits & 0x1ffff) == 0x120b)
         {
-          #include "insns/lhseg_v.h"
+          #include "insns/vlstbu.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x220b)
         {
-          #include "insns/lbuseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x108b)
-        {
-          #include "insns/lhst_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x128b)
-        {
-          #include "insns/lhust_v.h"
+          #include "insns/vlsegbu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1008b)
+        if((insn.bits & 0xfff) == 0xa8b)
         {
-          #include "insns/mov_sv.h"
+          #include "insns/vlsegsthu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1010b)
+        if((insn.bits & 0x1ffff) == 0x110b)
         {
-          #include "insns/mov_su.h"
+          #include "insns/vlstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x18b)
+        if((insn.bits & 0x1ffff) == 0x108b)
         {
-          #include "insns/ld_v.h"
+          #include "insns/vlsth.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d0b)
+        if((insn.bits & 0x1ffff) == 0x100b)
         {
-          #include "insns/fswst_v.h"
+          #include "insns/vlstb.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xd8b)
+        if((insn.bits & 0x1ffff) == 0x118b)
         {
-          #include "insns/fsd_v.h"
+          #include "insns/vlstd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1808b)
+        if((insn.bits & 0xfff) == 0xa0b)
         {
-          #include "insns/fmov_sv.h"
+          #include "insns/vlsegstbu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x2d8b)
+        if((insn.bits & 0x3fffff) == 0x28b)
         {
-          #include "insns/fsdseg_v.h"
+          #include "insns/vlhu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x190b)
+        if((insn.bits & 0xfff) == 0x90b)
         {
-          #include "insns/swst_v.h"
+          #include "insns/vlsegstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d8b)
+        if((insn.bits & 0x1ffff) == 0x130b)
         {
-          #include "insns/fsdst_v.h"
+          #include "insns/vlstwu.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xb)
+        if((insn.bits & 0xfff) == 0x80b)
         {
-          #include "insns/lb_v.h"
+          #include "insns/vlsegstb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x118b)
+        if((insn.bits & 0xfff) == 0x98b)
         {
-          #include "insns/ldst_v.h"
+          #include "insns/vlsegstd.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x258b)
         {
-          #include "insns/fldseg_v.h"
+          #include "insns/vflsegd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x8b)
-        {
-          #include "insns/lh_v.h"
-          break;
-        }
-        if((insn.bits & 0x3fffff) == 0x28b)
+        if((insn.bits & 0x1ffff) == 0x250b)
         {
-          #include "insns/lhu_v.h"
+          #include "insns/vflsegw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1018b)
+        if((insn.bits & 0xfff) == 0x88b)
         {
-          #include "insns/mov_us.h"
+          #include "insns/vlsegsth.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xd0b)
+        if((insn.bits & 0xfff) == 0xd0b)
         {
-          #include "insns/fsw_v.h"
+          #include "insns/vflsegstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x158b)
+        if((insn.bits & 0xfff) == 0xd8b)
         {
-          #include "insns/fldst_v.h"
+          #include "insns/vflsegstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x250b)
+        if((insn.bits & 0x3fffff) == 0x58b)
         {
-          #include "insns/flwseg_v.h"
+          #include "insns/vfld.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x200b)
+        if((insn.bits & 0x1ffff) == 0x230b)
         {
-          #include "insns/lbseg_v.h"
+          #include "insns/vlsegwu.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x50b)
         {
-          #include "insns/flw_v.h"
-          break;
-        }
-        if((insn.bits & 0x3fffff) == 0x90b)
-        {
-          #include "insns/sw_v.h"
+          #include "insns/vflw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x298b)
-        {
-          #include "insns/sdseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x130b)
+        if((insn.bits & 0x1ffff) == 0x200b)
         {
-          #include "insns/lwust_v.h"
+          #include "insns/vlsegb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x150b)
+        if((insn.bits & 0x1ffff) == 0x218b)
         {
-          #include "insns/flwst_v.h"
+          #include "insns/vlsegd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x88b)
+        if((insn.bits & 0x1ffff) == 0x208b)
         {
-          #include "insns/sh_v.h"
+          #include "insns/vlsegh.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x210b)
         {
-          #include "insns/lwseg_v.h"
-          break;
-        }
-        if((insn.bits & 0x1ffff) == 0x2d0b)
-        {
-          #include "insns/fswseg_v.h"
+          #include "insns/vlsegw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x288b)
+        if((insn.bits & 0x3fffff) == 0x20b)
         {
-          #include "insns/shseg_v.h"
+          #include "insns/vlbu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1818b)
+        if((insn.bits & 0x1ffff) == 0x228b)
         {
-          #include "insns/fmov_us.h"
+          #include "insns/vlseghu.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x228b)
+        throw trap_illegal_instruction;
+    break;
+  }
+  case 0xc:
+  {
+    #include "insns/c_sd.h"
+    break;
+  }
+  case 0xd:
+  {
+    #include "insns/c_sw.h"
+    break;
+  }
+  case 0xf:
+  {
+        if((insn.bits & 0x1ffff) == 0x150f)
         {
-          #include "insns/lhuseg_v.h"
+          #include "insns/vfsstw.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x120b)
+        if((insn.bits & 0xfff) == 0x90f)
         {
-          #include "insns/lbust_v.h"
+          #include "insns/vssegstw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x98b)
+        if((insn.bits & 0xfff) == 0x98f)
         {
-          #include "insns/sd_v.h"
+          #include "insns/vssegstd.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1000b)
+        if((insn.bits & 0xfff) == 0x80f)
         {
-          #include "insns/mov_vv.h"
+          #include "insns/vssegstb.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x110b)
+        if((insn.bits & 0xfff) == 0x88f)
         {
-          #include "insns/lwst_v.h"
+          #include "insns/vssegsth.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x198b)
+        if((insn.bits & 0x3fffff) == 0x10f)
         {
-          #include "insns/sdst_v.h"
+          #include "insns/vsw.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x1800b)
+        if((insn.bits & 0xfff) == 0xd8f)
         {
-          #include "insns/fmov_vv.h"
+          #include "insns/vfssegstd.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x188b)
+        if((insn.bits & 0x3fffff) == 0xf)
         {
-          #include "insns/shst_v.h"
+          #include "insns/vsb.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x80b)
+        if((insn.bits & 0x1ffff) == 0x110f)
         {
-          #include "insns/sb_v.h"
+          #include "insns/vsstw.h"
           break;
         }
-        throw trap_illegal_instruction;
-    break;
-  }
-  case 0xc:
-  {
-    #include "insns/c_sd.h"
-    break;
-  }
-  case 0xd:
-  {
-    #include "insns/c_sw.h"
-    break;
-  }
-  case 0xf:
-  {
-        if((insn.bits & 0xfff) == 0x20f)
+        if((insn.bits & 0x1ffff) == 0x108f)
         {
-          #include "insns/lbusegst_v.h"
+          #include "insns/vssth.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x18f)
+        if((insn.bits & 0x1ffff) == 0x100f)
         {
-          #include "insns/ldsegst_v.h"
+          #include "insns/vsstb.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x98f)
+        if((insn.bits & 0x1ffff) == 0x118f)
         {
-          #include "insns/sdsegst_v.h"
+          #include "insns/vsstd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x30f)
+        if((insn.bits & 0x1ffff) == 0x218f)
         {
-          #include "insns/lwusegst_v.h"
+          #include "insns/vssegd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x80f)
+        if((insn.bits & 0x1ffff) == 0x158f)
         {
-          #include "insns/sbsegst_v.h"
+          #include "insns/vfsstd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x58f)
+        if((insn.bits & 0xfff) == 0xd0f)
         {
-          #include "insns/fldsegst_v.h"
+          #include "insns/vfssegstw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x28f)
+        if((insn.bits & 0x1ffff) == 0x210f)
         {
-          #include "insns/lhusegst_v.h"
+          #include "insns/vssegw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xf)
+        if((insn.bits & 0x3fffff) == 0x18f)
         {
-          #include "insns/lbsegst_v.h"
+          #include "insns/vsd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xd8f)
+        if((insn.bits & 0x3fffff) == 0x8f)
         {
-          #include "insns/fsdsegst_v.h"
+          #include "insns/vsh.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0xd0f)
+        if((insn.bits & 0x1ffff) == 0x208f)
         {
-          #include "insns/fswsegst_v.h"
+          #include "insns/vssegh.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x88f)
+        if((insn.bits & 0x3fffff) == 0x50f)
         {
-          #include "insns/shsegst_v.h"
+          #include "insns/vfsw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x50f)
+        if((insn.bits & 0x3fffff) == 0x58f)
         {
-          #include "insns/flwsegst_v.h"
+          #include "insns/vfsd.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x10f)
+        if((insn.bits & 0x1ffff) == 0x250f)
         {
-          #include "insns/lwsegst_v.h"
+          #include "insns/vfssegw.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x90f)
+        if((insn.bits & 0x1ffff) == 0x200f)
         {
-          #include "insns/swsegst_v.h"
+          #include "insns/vssegb.h"
           break;
         }
-        if((insn.bits & 0xfff) == 0x8f)
+        if((insn.bits & 0x1ffff) == 0x258f)
         {
-          #include "insns/lhsegst_v.h"
+          #include "insns/vfssegd.h"
           break;
         }
         throw trap_illegal_instruction;
@@ -583,14 +543,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1063,14 +1023,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1493,11 +1453,6 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fsgnjn_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa053)
-        {
-          #include "insns/fcvt_w_s.h"
-          break;
-        }
         if((insn.bits & 0x3ff1ff) == 0xd0d3)
         {
           #include "insns/fcvt_d_lu.h"
@@ -1563,6 +1518,11 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/fsub_d.h"
           break;
         }
+        if((insn.bits & 0x3ff1ff) == 0xa053)
+        {
+          #include "insns/fcvt_w_s.h"
+          break;
+        }
         if((insn.bits & 0x3ff1ff) == 0x4053)
         {
           #include "insns/fsqrt_s.h"
@@ -1628,14 +1588,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)
@@ -1858,19 +1818,64 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0x73:
   {
-        if((insn.bits & 0x3ff) == 0x73)
+        if((insn.bits & 0x3ff) == 0xf3)
+        {
+          #include "insns/vvcfgivl.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x2f3)
         {
-          #include "insns/vcfgivl.h"
+          #include "insns/vsetvl.h"
           break;
         }
-        if((insn.bits & 0xf80003ff) == 0x173)
+        if((insn.bits & 0x1ffff) == 0x1173)
+        {
+          #include "insns/vfmst.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1973)
+        {
+          #include "insns/vfmts.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x973)
+        {
+          #include "insns/vfmsv.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1873)
+        {
+          #include "insns/vmts.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x73)
+        {
+          #include "insns/vmvv.h"
+          break;
+        }
+        if((insn.bits & 0x3ff) == 0x1f3)
+        {
+          #include "insns/vtcfgivl.h"
+          break;
+        }
+        if((insn.bits & 0xf80003ff) == 0x3f3)
         {
           #include "insns/vf.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xf3)
+        if((insn.bits & 0x3fffff) == 0x173)
+        {
+          #include "insns/vfmvv.h"
+          break;
+        }
+        if((insn.bits & 0x3fffff) == 0x873)
+        {
+          #include "insns/vmsv.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x1073)
         {
-          #include "insns/setvl.h"
+          #include "insns/vmst.h"
           break;
         }
         throw trap_illegal_instruction;
@@ -1893,9 +1898,14 @@ switch((insn.bits >> 0x0) & 0x7f)
   }
   case 0x77:
   {
-        if((insn.bits & 0x7ffffff) == 0x277)
+        if((insn.bits & 0x1ffff) == 0x2f7)
         {
-          #include "insns/rdcycle.h"
+          #include "insns/movn.h"
+          break;
+        }
+        if((insn.bits & 0x1ffff) == 0x277)
+        {
+          #include "insns/movz.h"
           break;
         }
         if((insn.bits & 0xffffffff) == 0x177)
@@ -1913,14 +1923,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/utidx.h"
           break;
         }
-        if((insn.bits & 0x7ffffff) == 0xa77)
+        if((insn.bits & 0x1ffff) == 0x3f7)
         {
-          #include "insns/rdinstret.h"
+          #include "insns/fmovn.h"
           break;
         }
-        if((insn.bits & 0x7ffffff) == 0x677)
+        if((insn.bits & 0x1ffff) == 0x377)
         {
-          #include "insns/rdtime.h"
+          #include "insns/fmovz.h"
           break;
         }
         if((insn.bits & 0xffffffff) == 0x77)
@@ -1953,14 +1963,14 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/c_srai32.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0xc19)
+        if((insn.bits & 0x1c1f) == 0x1819)
         {
-          #include "insns/c_srli32.h"
+          #include "insns/c_slliw.h"
           break;
         }
-        if((insn.bits & 0x1c1f) == 0x1819)
+        if((insn.bits & 0x1c1f) == 0xc19)
         {
-          #include "insns/c_slliw.h"
+          #include "insns/c_srli32.h"
           break;
         }
         if((insn.bits & 0x1c1f) == 0x1019)

diff --git a/riscv/insns/fld_v.h b/riscv/insns/fld_v.h
deleted file mode 100644 (file)
index 9b40470..0000000
--- a/riscv/insns/fld_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, 8);

diff --git a/riscv/insns/fldseg_v.h b/riscv/insns/fldseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fldsegst_v.h b/riscv/insns/fldsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fldst_v.h b/riscv/insns/fldst_v.h
deleted file mode 100644 (file)
index fa9b32d..0000000
--- a/riscv/insns/fldst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int64, RS2);

diff --git a/riscv/insns/flw_v.h b/riscv/insns/flw_v.h
deleted file mode 100644 (file)
index 75fdd04..0000000
--- a/riscv/insns/flw_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, 4);

diff --git a/riscv/insns/flwseg_v.h b/riscv/insns/flwseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/flwsegst_v.h b/riscv/insns/flwsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/flwst_v.h b/riscv/insns/flwst_v.h
deleted file mode 100644 (file)
index 716c818..0000000
--- a/riscv/insns/flwst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_LOAD(FRD, load_int32, RS2);

diff --git a/riscv/insns/fmov_su.h b/riscv/insns/fmov_su.h
deleted file mode 100644 (file)
index 20fa123..0000000
--- a/riscv/insns/fmov_su.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
-UT_FRD(RS2) = FRS1;

diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/fmov_sv.h
deleted file mode 100644 (file)
index a9aa876..0000000
--- a/riscv/insns/fmov_sv.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = FRS1;
-UT_LOOP_END

diff --git a/riscv/insns/fmov_us.h b/riscv/insns/fmov_us.h
deleted file mode 100644 (file)
index 6f56b25..0000000
--- a/riscv/insns/fmov_us.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-require_fp;
-demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
-FRD = UT_FRS1(RS2);

diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h
deleted file mode 100644 (file)
index 279da21..0000000
--- a/riscv/insns/fmov_vv.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_vector;
-require_fp;
-UT_LOOP_START
-  UT_LOOP_FRD = UT_LOOP_FRS1;
-UT_LOOP_END

diff --git a/riscv/insns/fmovn.h b/riscv/insns/fmovn.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/fmovz.h b/riscv/insns/fmovz.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/fsd_v.h b/riscv/insns/fsd_v.h
deleted file mode 100644 (file)
index f619fc8..0000000
--- a/riscv/insns/fsd_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, 8);

diff --git a/riscv/insns/fsdseg_v.h b/riscv/insns/fsdseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsdsegst_v.h b/riscv/insns/fsdsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/fsdst_v.h
deleted file mode 100644 (file)
index b3bb260..0000000
--- a/riscv/insns/fsdst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint64, RS2);

diff --git a/riscv/insns/fsw_v.h b/riscv/insns/fsw_v.h
deleted file mode 100644 (file)
index 3fe3d3f..0000000
--- a/riscv/insns/fsw_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, 4);

diff --git a/riscv/insns/fswseg_v.h b/riscv/insns/fswseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fswsegst_v.h b/riscv/insns/fswsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/fswst_v.h b/riscv/insns/fswst_v.h
deleted file mode 100644 (file)
index 9cef9b0..0000000
--- a/riscv/insns/fswst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_fp;
-VEC_STORE(FRD, store_uint32, RS2);

diff --git a/riscv/insns/lb_v.h b/riscv/insns/lb_v.h
deleted file mode 100644 (file)
index 618380a..0000000
--- a/riscv/insns/lb_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, 1);

diff --git a/riscv/insns/lbseg_v.h b/riscv/insns/lbseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lbsegst_v.h b/riscv/insns/lbsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lbst_v.h b/riscv/insns/lbst_v.h
deleted file mode 100644 (file)
index 219d90e..0000000
--- a/riscv/insns/lbst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int8, RS2);

diff --git a/riscv/insns/lbu_v.h b/riscv/insns/lbu_v.h
deleted file mode 100644 (file)
index f92c8b5..0000000
--- a/riscv/insns/lbu_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, 1);

diff --git a/riscv/insns/lbuseg_v.h b/riscv/insns/lbuseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lbusegst_v.h b/riscv/insns/lbusegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lbust_v.h b/riscv/insns/lbust_v.h
deleted file mode 100644 (file)
index 09faa29..0000000
--- a/riscv/insns/lbust_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint8, RS2);

diff --git a/riscv/insns/ld_v.h b/riscv/insns/ld_v.h
deleted file mode 100644 (file)
index fb7a3c5..0000000
--- a/riscv/insns/ld_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, 8);

diff --git a/riscv/insns/ldseg_v.h b/riscv/insns/ldseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/ldsegst_v.h b/riscv/insns/ldsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/ldst_v.h b/riscv/insns/ldst_v.h
deleted file mode 100644 (file)
index 5e5de9c..0000000
--- a/riscv/insns/ldst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_LOAD(RD, load_int64, RS2);

diff --git a/riscv/insns/lh_v.h b/riscv/insns/lh_v.h
deleted file mode 100644 (file)
index 269c2a8..0000000
--- a/riscv/insns/lh_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, 2);

diff --git a/riscv/insns/lhseg_v.h b/riscv/insns/lhseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lhsegst_v.h b/riscv/insns/lhsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lhst_v.h b/riscv/insns/lhst_v.h
deleted file mode 100644 (file)
index af6b5b5..0000000
--- a/riscv/insns/lhst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int16, RS2);

diff --git a/riscv/insns/lhu_v.h b/riscv/insns/lhu_v.h
deleted file mode 100644 (file)
index 7a2019d..0000000
--- a/riscv/insns/lhu_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, 2);

diff --git a/riscv/insns/lhuseg_v.h b/riscv/insns/lhuseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lhusegst_v.h b/riscv/insns/lhusegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lhust_v.h b/riscv/insns/lhust_v.h
deleted file mode 100644 (file)
index 0fe8452..0000000
--- a/riscv/insns/lhust_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint16, RS2);

diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
deleted file mode 100644 (file)
index 6e35911..0000000
--- a/riscv/insns/lw_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, 4);

diff --git a/riscv/insns/lwseg_v.h b/riscv/insns/lwseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lwsegst_v.h b/riscv/insns/lwsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
deleted file mode 100644 (file)
index 5375dc0..0000000
--- a/riscv/insns/lwst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_int32, RS2);

diff --git a/riscv/insns/lwu_v.h b/riscv/insns/lwu_v.h
deleted file mode 100644 (file)
index 4fa1489..0000000
--- a/riscv/insns/lwu_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, 4);

diff --git a/riscv/insns/lwuseg_v.h b/riscv/insns/lwuseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lwusegst_v.h b/riscv/insns/lwusegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/lwust_v.h b/riscv/insns/lwust_v.h
deleted file mode 100644 (file)
index 328e23f..0000000
--- a/riscv/insns/lwust_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_LOAD(RD, load_uint32, RS2);

diff --git a/riscv/insns/mov_su.h b/riscv/insns/mov_su.h
deleted file mode 100644 (file)
index 7b7cae1..0000000
--- a/riscv/insns/mov_su.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
-UT_RD(RS2) = RS1;

diff --git a/riscv/insns/mov_sv.h b/riscv/insns/mov_sv.h
deleted file mode 100644 (file)
index c6f4c2c..0000000
--- a/riscv/insns/mov_sv.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = RS1;
-UT_LOOP_END

diff --git a/riscv/insns/mov_us.h b/riscv/insns/mov_us.h
deleted file mode 100644 (file)
index a69e388..0000000
--- a/riscv/insns/mov_us.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
-RD = UT_RS1(RS2);

diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h
deleted file mode 100644 (file)
index 91d63d4..0000000
--- a/riscv/insns/mov_vv.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_vector;
-UT_LOOP_START
-  UT_LOOP_RD = UT_LOOP_RS1;
-UT_LOOP_END

diff --git a/riscv/insns/movn.h b/riscv/insns/movn.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/movz.h b/riscv/insns/movz.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/sb_v.h b/riscv/insns/sb_v.h
deleted file mode 100644 (file)
index c3d5b9d..0000000
--- a/riscv/insns/sb_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, 1);

diff --git a/riscv/insns/sbseg_v.h b/riscv/insns/sbseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/sbsegst_v.h b/riscv/insns/sbsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/sbst_v.h b/riscv/insns/sbst_v.h
deleted file mode 100644 (file)
index b83cc50..0000000
--- a/riscv/insns/sbst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint8, RS2);

diff --git a/riscv/insns/sd_v.h b/riscv/insns/sd_v.h
deleted file mode 100644 (file)
index 9c02069..0000000
--- a/riscv/insns/sd_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, 8);

diff --git a/riscv/insns/sdseg_v.h b/riscv/insns/sdseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/sdsegst_v.h b/riscv/insns/sdsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/sdst_v.h b/riscv/insns/sdst_v.h
deleted file mode 100644 (file)
index 26868d2..0000000
--- a/riscv/insns/sdst_v.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-require_xpr64;
-VEC_STORE(RD, store_uint64, RS2);

diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
deleted file mode 100644 (file)
index c2212ff..0000000
--- a/riscv/insns/setvl.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_vector;
-setvl(RS1);
-RD = VL;

diff --git a/riscv/insns/sh_v.h b/riscv/insns/sh_v.h
deleted file mode 100644 (file)
index 623eda8..0000000
--- a/riscv/insns/sh_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, 2);

diff --git a/riscv/insns/shseg_v.h b/riscv/insns/shseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/shsegst_v.h b/riscv/insns/shsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/shst_v.h b/riscv/insns/shst_v.h
deleted file mode 100644 (file)
index 3904331..0000000
--- a/riscv/insns/shst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint16, RS2);

diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
deleted file mode 100644 (file)
index 662d4e3..0000000
--- a/riscv/insns/sw_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, 4);

diff --git a/riscv/insns/swseg_v.h b/riscv/insns/swseg_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/swsegst_v.h b/riscv/insns/swsegst_v.h
deleted file mode 100644 (file)
index e69de29..0000000

diff --git a/riscv/insns/swst_v.h b/riscv/insns/swst_v.h
deleted file mode 100644 (file)
index 8f05953..0000000
--- a/riscv/insns/swst_v.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_vector;
-VEC_STORE(RD, store_uint32, RS2);

diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h
deleted file mode 100644 (file)
index 0ded9f8..0000000
--- a/riscv/insns/vcfgivl.h
+++ /dev/null
@@ -1,6 +0,0 @@
-require_vector;
-nxpr_use = SIMM & 0x3f;
-nfpr_use = (SIMM >> 6) & 0x3f;
-vcfg();
-setvl(RS1);
-RD = VL;

diff --git a/riscv/insns/vfld.h b/riscv/insns/vfld.h
new file mode 100644 (file)
index 0000000..9b40470
--- /dev/null
+++ b/riscv/insns/vfld.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_LOAD(FRD, load_int64, 8);

diff --git a/riscv/insns/vflsegd.h b/riscv/insns/vflsegd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vflsegstd.h b/riscv/insns/vflsegstd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vflsegstw.h b/riscv/insns/vflsegstw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vflsegw.h b/riscv/insns/vflsegw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vflstd.h b/riscv/insns/vflstd.h
new file mode 100644 (file)
index 0000000..fa9b32d
--- /dev/null
+++ b/riscv/insns/vflstd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_LOAD(FRD, load_int64, RS2);

diff --git a/riscv/insns/vflstw.h b/riscv/insns/vflstw.h
new file mode 100644 (file)
index 0000000..716c818
--- /dev/null
+++ b/riscv/insns/vflstw.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_LOAD(FRD, load_int32, RS2);

diff --git a/riscv/insns/vflw.h b/riscv/insns/vflw.h
new file mode 100644 (file)
index 0000000..75fdd04
--- /dev/null
+++ b/riscv/insns/vflw.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_LOAD(FRD, load_int32, 4);

diff --git a/riscv/insns/vfmst.h b/riscv/insns/vfmst.h
new file mode 100644 (file)
index 0000000..20fa123
--- /dev/null
+++ b/riscv/insns/vfmst.h
@@ -0,0 +1,4 @@
+require_vector;
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_FRD(RS2) = FRS1;

diff --git a/riscv/insns/vfmsv.h b/riscv/insns/vfmsv.h
new file mode 100644 (file)
index 0000000..a9aa876
--- /dev/null
+++ b/riscv/insns/vfmsv.h
@@ -0,0 +1,5 @@
+require_vector;
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = FRS1;
+UT_LOOP_END

diff --git a/riscv/insns/vfmts.h b/riscv/insns/vfmts.h
new file mode 100644 (file)
index 0000000..6f56b25
--- /dev/null
+++ b/riscv/insns/vfmts.h
@@ -0,0 +1,4 @@
+require_vector;
+require_fp;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+FRD = UT_FRS1(RS2);

diff --git a/riscv/insns/vfmvv.h b/riscv/insns/vfmvv.h
new file mode 100644 (file)
index 0000000..279da21
--- /dev/null
+++ b/riscv/insns/vfmvv.h
@@ -0,0 +1,5 @@
+require_vector;
+require_fp;
+UT_LOOP_START
+  UT_LOOP_FRD = UT_LOOP_FRS1;
+UT_LOOP_END

diff --git a/riscv/insns/vfsd.h b/riscv/insns/vfsd.h
new file mode 100644 (file)
index 0000000..f619fc8
--- /dev/null
+++ b/riscv/insns/vfsd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_STORE(FRD, store_uint64, 8);

diff --git a/riscv/insns/vfssegd.h b/riscv/insns/vfssegd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vfssegstd.h b/riscv/insns/vfssegstd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vfssegstw.h b/riscv/insns/vfssegstw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vfssegw.h b/riscv/insns/vfssegw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vfsstd.h b/riscv/insns/vfsstd.h
new file mode 100644 (file)
index 0000000..b3bb260
--- /dev/null
+++ b/riscv/insns/vfsstd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_STORE(FRD, store_uint64, RS2);

diff --git a/riscv/insns/vfsstw.h b/riscv/insns/vfsstw.h
new file mode 100644 (file)
index 0000000..9cef9b0
--- /dev/null
+++ b/riscv/insns/vfsstw.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_STORE(FRD, store_uint32, RS2);

diff --git a/riscv/insns/vfsw.h b/riscv/insns/vfsw.h
new file mode 100644 (file)
index 0000000..3fe3d3f
--- /dev/null
+++ b/riscv/insns/vfsw.h
@@ -0,0 +1,3 @@
+require_vector;
+require_fp;
+VEC_STORE(FRD, store_uint32, 4);

diff --git a/riscv/insns/vlb.h b/riscv/insns/vlb.h
new file mode 100644 (file)
index 0000000..618380a
--- /dev/null
+++ b/riscv/insns/vlb.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int8, 1);

diff --git a/riscv/insns/vlbu.h b/riscv/insns/vlbu.h
new file mode 100644 (file)
index 0000000..f92c8b5
--- /dev/null
+++ b/riscv/insns/vlbu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint8, 1);

diff --git a/riscv/insns/vld.h b/riscv/insns/vld.h
new file mode 100644 (file)
index 0000000..fb7a3c5
--- /dev/null
+++ b/riscv/insns/vld.h
@@ -0,0 +1,3 @@
+require_vector;
+require_xpr64;
+VEC_LOAD(RD, load_int64, 8);

diff --git a/riscv/insns/vlh.h b/riscv/insns/vlh.h
new file mode 100644 (file)
index 0000000..269c2a8
--- /dev/null
+++ b/riscv/insns/vlh.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int16, 2);

diff --git a/riscv/insns/vlhu.h b/riscv/insns/vlhu.h
new file mode 100644 (file)
index 0000000..7a2019d
--- /dev/null
+++ b/riscv/insns/vlhu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint16, 2);

diff --git a/riscv/insns/vlsegb.h b/riscv/insns/vlsegb.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegbu.h b/riscv/insns/vlsegbu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegd.h b/riscv/insns/vlsegd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegh.h b/riscv/insns/vlsegh.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlseghu.h b/riscv/insns/vlseghu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegstb.h b/riscv/insns/vlsegstb.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegstbu.h b/riscv/insns/vlsegstbu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegstd.h b/riscv/insns/vlsegstd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegsth.h b/riscv/insns/vlsegsth.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegsthu.h b/riscv/insns/vlsegsthu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegstw.h b/riscv/insns/vlsegstw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegstwu.h b/riscv/insns/vlsegstwu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegw.h b/riscv/insns/vlsegw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlsegwu.h b/riscv/insns/vlsegwu.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vlstb.h b/riscv/insns/vlstb.h
new file mode 100644 (file)
index 0000000..219d90e
--- /dev/null
+++ b/riscv/insns/vlstb.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int8, RS2);

diff --git a/riscv/insns/vlstbu.h b/riscv/insns/vlstbu.h
new file mode 100644 (file)
index 0000000..09faa29
--- /dev/null
+++ b/riscv/insns/vlstbu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint8, RS2);

diff --git a/riscv/insns/vlstd.h b/riscv/insns/vlstd.h
new file mode 100644 (file)
index 0000000..5e5de9c
--- /dev/null
+++ b/riscv/insns/vlstd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_xpr64;
+VEC_LOAD(RD, load_int64, RS2);

diff --git a/riscv/insns/vlsth.h b/riscv/insns/vlsth.h
new file mode 100644 (file)
index 0000000..af6b5b5
--- /dev/null
+++ b/riscv/insns/vlsth.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int16, RS2);

diff --git a/riscv/insns/vlsthu.h b/riscv/insns/vlsthu.h
new file mode 100644 (file)
index 0000000..0fe8452
--- /dev/null
+++ b/riscv/insns/vlsthu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint16, RS2);

diff --git a/riscv/insns/vlstw.h b/riscv/insns/vlstw.h
new file mode 100644 (file)
index 0000000..5375dc0
--- /dev/null
+++ b/riscv/insns/vlstw.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int32, RS2);

diff --git a/riscv/insns/vlstwu.h b/riscv/insns/vlstwu.h
new file mode 100644 (file)
index 0000000..328e23f
--- /dev/null
+++ b/riscv/insns/vlstwu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint32, RS2);

diff --git a/riscv/insns/vlw.h b/riscv/insns/vlw.h
new file mode 100644 (file)
index 0000000..6e35911
--- /dev/null
+++ b/riscv/insns/vlw.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_int32, 4);

diff --git a/riscv/insns/vlwu.h b/riscv/insns/vlwu.h
new file mode 100644 (file)
index 0000000..4fa1489
--- /dev/null
+++ b/riscv/insns/vlwu.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_LOAD(RD, load_uint32, 4);

diff --git a/riscv/insns/vmst.h b/riscv/insns/vmst.h
new file mode 100644 (file)
index 0000000..7b7cae1
--- /dev/null
+++ b/riscv/insns/vmst.h
@@ -0,0 +1,3 @@
+require_vector;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
+UT_RD(RS2) = RS1;

diff --git a/riscv/insns/vmsv.h b/riscv/insns/vmsv.h
new file mode 100644 (file)
index 0000000..c6f4c2c
--- /dev/null
+++ b/riscv/insns/vmsv.h
@@ -0,0 +1,4 @@
+require_vector;
+UT_LOOP_START
+  UT_LOOP_RD = RS1;
+UT_LOOP_END

diff --git a/riscv/insns/vmts.h b/riscv/insns/vmts.h
new file mode 100644 (file)
index 0000000..a69e388
--- /dev/null
+++ b/riscv/insns/vmts.h
@@ -0,0 +1,3 @@
+require_vector;
+demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
+RD = UT_RS1(RS2);

diff --git a/riscv/insns/vmvv.h b/riscv/insns/vmvv.h
new file mode 100644 (file)
index 0000000..91d63d4
--- /dev/null
+++ b/riscv/insns/vmvv.h
@@ -0,0 +1,4 @@
+require_vector;
+UT_LOOP_START
+  UT_LOOP_RD = UT_LOOP_RS1;
+UT_LOOP_END

diff --git a/riscv/insns/vsb.h b/riscv/insns/vsb.h
new file mode 100644 (file)
index 0000000..c3d5b9d
--- /dev/null
+++ b/riscv/insns/vsb.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint8, 1);

diff --git a/riscv/insns/vsd.h b/riscv/insns/vsd.h
new file mode 100644 (file)
index 0000000..9c02069
--- /dev/null
+++ b/riscv/insns/vsd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_xpr64;
+VEC_STORE(RD, store_uint64, 8);

diff --git a/riscv/insns/vsetvl.h b/riscv/insns/vsetvl.h
new file mode 100644 (file)
index 0000000..c2212ff
--- /dev/null
+++ b/riscv/insns/vsetvl.h
@@ -0,0 +1,3 @@
+require_vector;
+setvl(RS1);
+RD = VL;

diff --git a/riscv/insns/vsh.h b/riscv/insns/vsh.h
new file mode 100644 (file)
index 0000000..623eda8
--- /dev/null
+++ b/riscv/insns/vsh.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint16, 2);

diff --git a/riscv/insns/vssegb.h b/riscv/insns/vssegb.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegd.h b/riscv/insns/vssegd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegh.h b/riscv/insns/vssegh.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegstb.h b/riscv/insns/vssegstb.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegstd.h b/riscv/insns/vssegstd.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegsth.h b/riscv/insns/vssegsth.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegstw.h b/riscv/insns/vssegstw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vssegw.h b/riscv/insns/vssegw.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vsstb.h b/riscv/insns/vsstb.h
new file mode 100644 (file)
index 0000000..b83cc50
--- /dev/null
+++ b/riscv/insns/vsstb.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint8, RS2);

diff --git a/riscv/insns/vsstd.h b/riscv/insns/vsstd.h
new file mode 100644 (file)
index 0000000..26868d2
--- /dev/null
+++ b/riscv/insns/vsstd.h
@@ -0,0 +1,3 @@
+require_vector;
+require_xpr64;
+VEC_STORE(RD, store_uint64, RS2);

diff --git a/riscv/insns/vssth.h b/riscv/insns/vssth.h
new file mode 100644 (file)
index 0000000..3904331
--- /dev/null
+++ b/riscv/insns/vssth.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint16, RS2);

diff --git a/riscv/insns/vsstw.h b/riscv/insns/vsstw.h
new file mode 100644 (file)
index 0000000..8f05953
--- /dev/null
+++ b/riscv/insns/vsstw.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint32, RS2);

diff --git a/riscv/insns/vsw.h b/riscv/insns/vsw.h
new file mode 100644 (file)
index 0000000..662d4e3
--- /dev/null
+++ b/riscv/insns/vsw.h
@@ -0,0 +1,2 @@
+require_vector;
+VEC_STORE(RD, store_uint32, 4);

diff --git a/riscv/insns/vtcfgivl.h b/riscv/insns/vtcfgivl.h
new file mode 100644 (file)
index 0000000..e69de29

diff --git a/riscv/insns/vvcfgivl.h b/riscv/insns/vvcfgivl.h
new file mode 100644 (file)
index 0000000..0ded9f8
--- /dev/null
+++ b/riscv/insns/vvcfgivl.h
@@ -0,0 +1,6 @@
+require_vector;
+nxpr_use = SIMM & 0x3f;
+nfpr_use = (SIMM >> 6) & 0x3f;
+vcfg();
+setvl(RS1);
+RD = VL;