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Implement transparent read ports on the phased write SRAM
authorCesar Strauss <cestrauss@gmail.com>
Sat, 2 Apr 2022 20:46:29 +0000 (17:46 -0300)
committerCesar Strauss <cestrauss@gmail.com>
Sat, 2 Apr 2022 20:46:29 +0000 (17:46 -0300)
Add a multiplexer to select the write memory instead of the read
memory, in case both port addresses coincide.


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