Merge branch 'master' of /project/eecs/parlab/git/projects/riscv

Conflicts:
	sim/riscv/insns/mtpcr.h
	sim/riscv/processor.cc

diff --git a/riscv/decode.h b/riscv/decode.h
index dffb9bef50541afbc3403f3f4d8f5b3c1331167e..a5ea4bc9e963b63f42710a77c7e760ade85287c8 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -36,9 +36,11 @@ const int JUMP_ALIGN_BITS = 1;
 #define SR_S     0x0000000000000008ULL
 #define SR_EF    0x0000000000000010ULL
 #define SR_UX    0x0000000000000020ULL
-#define SR_KX    0x0000000000000040ULL
+#define SR_SX    0x0000000000000040ULL
 #define SR_IM    0x000000000000FF00ULL
-#define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_KX | SR_IM)
+#define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
+#define SR_IM_SHIFT 8
+#define TIMER_IRQ 7
 
 #define FP_RD_NE  0
 #define FP_RD_0   1

diff --git a/riscv/insns/mfcr.h b/riscv/insns/mfcr.h
index 7ce1d9ee79a195a20a9a0ac63eae50f5dd87a91b..088480cba7e4f18c96b5998a98284084df67cf25 100644 (file)
--- a/riscv/insns/mfcr.h
+++ b/riscv/insns/mfcr.h
@@ -2,6 +2,10 @@ reg_t val;
 
 switch(insn.rtype.rb)
 {
+  case 0:
+    val = fsr;
+    break;
+
   case 1:
     val = 32; // synci_step
     break;

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 94ce2b2a86debfaee3a29f37bdadb3d96b5e0963..3416db1f870674f6c4dc2a414e9fe6fa783a7c97 100644 (file)
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -16,6 +16,12 @@ switch(insn.rtype.rb)
   case 3:
     val = ebase;
     break;
+  case 4:
+    val = count;
+    break;
+  case 5:
+    val = compare;
+    break;
 
   case 8:
     val = MEMSIZE >> 12;

diff --git a/riscv/insns/mtcr.h b/riscv/insns/mtcr.h
index 5f85a51abcd3853cc12c5b3178b4d119d3634856..d7b2b17eb2b1c9d6c689528ad0357da562f46bb9 100644 (file)
--- a/riscv/insns/mtcr.h
+++ b/riscv/insns/mtcr.h
@@ -1,8 +1,10 @@
-reg_t val = gprlen == 64 ? RA : sext32(RA);
-
 switch(insn.rtype.rb)
 {
+  case 0:
+    set_fsr(RA);
+    break;
+
   case 29:
-    tid = val;
+    tid = RA;
     break;
 }

diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 5c7289eb7097f4366240278425ac872247d9a9aa..79e28bf4c5c44a36f6bd7a86abef0c523b844657 100644 (file)
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,28 +1,33 @@
 require_supervisor;
 
-reg_t val = gprlen == 64 ? RA : sext32(RA);
-
 switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(val);
+    set_sr(RA);
     break;
   case 1:
-    epc = val;
+    epc = RA;
     break;
   case 3:
-    ebase = val & ~0xFFF;
+    ebase = RA & ~0xFFF;
+    break;
+  case 4:
+    count = RA;
+    break;
+  case 5:
+    interrupts_pending &= ~(1 << TIMER_IRQ);
+    compare = RA;
     break;
 
   case 16:
-    tohost = val;
-    sim->set_tohost(tohost);
+    tohost = RA;
+    sim->set_tohost(RA);
     break;
 
   case 24:
-    pcr_k0 = val;
+    pcr_k0 = RA;
     break;
   case 25:
-    pcr_k1 = val;
+    pcr_k1 = RA;
     break;
 }

diff --git a/riscv/processor.cc b/riscv/processor.cc
index e336aa1990113b736aa0c10055dfdedc1a9e5596..271afbf0115652af627073b693c1d1858a4f3a5c 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -23,7 +23,10 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   pcr_k1 = 0;
   tohost = 0;
   fromhost = 0;
-  set_sr(SR_S | (support_64bit ? SR_KX : 0));
+  count = 0;
+  compare = 0;
+  interrupts_pending = 0;
+  set_sr(SR_S | (support_64bit ? SR_SX : 0));
   set_fsr(0);
 
   memset(counters,0,sizeof(counters));
@@ -46,14 +49,15 @@ void processor_t::set_sr(uint32_t val)
 {
   sr = val & ~SR_ZERO;
   if(!support_64bit)
-    sr &= ~(SR_KX | SR_UX);
+    sr &= ~(SR_SX | SR_UX);
 
-  gprlen = ((sr & SR_S) ? (sr & SR_KX) : (sr & SR_UX)) ? 64 : 32;
+  gprlen = ((sr & SR_S) ? (sr & SR_SX) : (sr & SR_UX)) ? 64 : 32;
 }
 
 void processor_t::set_fsr(uint32_t val)
 {
   fsr = val & ~FSR_ZERO;
+  softfloat_roundingMode = (fsr & FSR_RD) >> FSR_RD_SHIFT;
 }
 
 void processor_t::step(size_t n, bool noisy)
@@ -63,6 +67,14 @@ void processor_t::step(size_t n, bool noisy)
   {
     for( ; i < n; i++)
     {
+      uint32_t interrupts = interrupts_pending & ((sr & SR_IM) >> SR_IM_SHIFT);
+      if((sr & SR_ET) && interrupts)
+      {
+        for(int i = 0; interrupts; i++, interrupts >>= 1)
+          if(interrupts & 1)
+            throw trap_t(16+i);
+      }
+
       insn_t insn = mmu.load_insn(pc);
   
       reg_t npc = pc+sizeof(insn);
@@ -75,7 +87,8 @@ void processor_t::step(size_t n, bool noisy)
       pc = npc;
       R[0] = 0;
 
-      counters[0]++;
+      if(count++ == compare)
+        interrupts_pending |= 1 << TIMER_IRQ;
     }
     return;
   }

diff --git a/riscv/processor.h b/riscv/processor.h
index 4a1a41da2350228e6c39d0c838450eb0392c8143..fab6c9ceb996897833045e087d7115b14a8f8bc1 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -33,6 +33,9 @@ private:
   reg_t pcr_k1;
   uint32_t id;
   uint32_t sr;
+  uint32_t count;
+  uint32_t compare;
+  uint32_t interrupts_pending;
 
   // unprivileged control registers
   uint32_t tid;