add near-duplicate of SV CFG REG CSRs, for predication

diff --git a/riscv/processor.cc b/riscv/processor.cc
index f353c8b9eb3d0d59a358203510e7e97742ae2128..b5ae0993a5201ddb53006fb20230eb3986db426d 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -394,6 +394,47 @@ void processor_t::set_csr(int which, reg_t val)
       }
       break;
     }
+    case CSR_SVPREDCFG0:
+    case CSR_SVPREDCFG1:
+    case CSR_SVPREDCFG2:
+    case CSR_SVPREDCFG3:
+    case CSR_SVPREDCFG4:
+    case CSR_SVPREDCFG5:
+    case CSR_SVPREDCFG6:
+    case CSR_SVPREDCFG7:
+    {
+      // comments removed as it's near-identical to the regs version
+      // TODO: macro-ify
+      int tbidx = (which - CSR_SVPREDCFG0) * 2;
+      state.sv_pred_csrs[tbidx].u = get_field(val, 0xffff);
+      state.sv_pred_csrs[tbidx+1].u = get_field(val, 0xffff0000);
+      for (int i = tbidx+2; i < 16; i++)
+      {
+          state.sv_pred_csrs[i].u = 0;
+      }
+      memset(state.sv_int_tb, 0, sizeof(state.sv_int_tb));
+      memset(state.sv_fp_tb, 0, sizeof(state.sv_fp_tb));
+      for (int i = 0; i < SV_CSR_SZ; i++)
+      {
+        union sv_pred_csr_entry *c = &state.sv_pred_csrs[i];
+        uint64_t idx = c->b.regidx;
+        sv_pred_entry *r;
+        // XXX damn.  this basically duplicates sv_insn_t::get_predentry.
+        if (c->b.type == 1)
+        {
+            r = &state.sv_pred_int_tb[idx];
+        }
+        else
+        {
+            r = &state.sv_pred_int_tb[idx];
+        }
+        r->regidx = c->b.regidx;
+        r->zero   = c->b.zero;
+        r->inv    = c->b.inv;
+        r->active = true;
+      }
+      break;
+    }
 #endif
     case CSR_FFLAGS:
       dirty_fp_state;