Add in remaining fields from major decoder

diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py
index b305cf594f172ba9210003f4844b611b348a0fbf..d3078444129e1b1e5f3c5c94de17b392a211b57c 100644 (file)
--- a/src/decoder/power_major_decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -60,6 +60,21 @@ class OutSel(Enum):
     SPR = 3
 
 
+@unique
+class LdstLen(Enum):
+    NONE = 0
+    is1B = 1
+    is2B = 2
+    is4B = 3
+
+
+@unique
+class RC(Enum):
+    NONE = 0
+    ONE = 1
+    RC = 2
+
+
 # names of the fields in major.csv that don't correspond to an enum
 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', 'cry in',
                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
@@ -90,6 +105,8 @@ class PowerMajorDecoder(Elaboratable):
         self.in2_sel = Signal(In2Sel, reset_less=True)
         self.in3_sel = Signal(In3Sel, reset_less=True)
         self.out_sel = Signal(OutSel, reset_less=True)
+        self.ldst_len = Signal(LdstLen, reset_less=True)
+        self.rc_sel = Signal(RC, reset_less=True)
         for bit in single_bit_flags:
             name = get_signal_name(bit)
             setattr(self, name,
@@ -109,6 +126,8 @@ class PowerMajorDecoder(Elaboratable):
                     comb += self.in2_sel.eq(In2Sel[row['in2']])
                     comb += self.in3_sel.eq(In3Sel[row['in3']])
                     comb += self.out_sel.eq(OutSel[row['out']])
+                    comb += self.ldst_len.eq(LdstLen[row['ldst len']])
+                    comb += self.rc_sel.eq(RC[row['rc']])
                     for bit in single_bit_flags:
                         sig = getattr(self, get_signal_name(bit))
                         comb += sig.eq(int(row[bit]))
@@ -121,6 +140,8 @@ class PowerMajorDecoder(Elaboratable):
                   self.in2_sel,
                   self.in3_sel,
                   self.out_sel,
+                  self.ldst_len,
+                  self.rc_sel,
                   self.internal_op]
         single_bit_ports = [getattr(self, get_signal_name(x))
                             for x in single_bit_flags]

diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index 84c8d50e556ef77404ad818ddbd823f52eacb568..7ef62b13f48848dc40ca5a228eb7734b5a2e24e7 100644 (file)
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -7,6 +7,7 @@ import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
                                  In1Sel, In2Sel, In3Sel, OutSel,
+                                 LdstLen, RC,
                                  single_bit_flags, get_signal_name,
                                  InternalOp, major_opcodes)
 
@@ -22,6 +23,8 @@ class DecoderTestCase(FHDLTestCase):
         in2_sel = Signal(In2Sel)
         in3_sel = Signal(In3Sel)
         out_sel = Signal(OutSel)
+        rc_sel = Signal(RC)
+        ldst_len = Signal(LdstLen)
 
         m.submodules.dut = dut = PowerMajorDecoder()
         comb += [dut.opcode_in.eq(opcode),
@@ -30,6 +33,8 @@ class DecoderTestCase(FHDLTestCase):
                  in2_sel.eq(dut.in2_sel),
                  in3_sel.eq(dut.in3_sel),
                  out_sel.eq(dut.out_sel),
+                 rc_sel.eq(dut.rc_sel),
+                 ldst_len.eq(dut.ldst_len),
                  internal_op.eq(dut.internal_op)]
 
         sim = Simulator(m)
@@ -62,6 +67,14 @@ class DecoderTestCase(FHDLTestCase):
                 expected = OutSel[row['out']].value
                 self.assertEqual(expected, result)
 
+                result = yield rc_sel
+                expected = RC[row['rc']].value
+                self.assertEqual(expected, result)
+
+                result = yield ldst_len
+                expected = LdstLen[row['ldst len']].value
+                self.assertEqual(expected, result)
+
                 for bit in single_bit_flags:
                     sig = getattr(dut, get_signal_name(bit))
                     result = yield sig