Add signals for single bit flags in major.csv

diff --git a/src/decoder/major.csv b/src/decoder/major.csv
index f58784a6b9ee0f30fd72ededddee7b1d22f14df9..f9f7cfceb7acbad98181a6c01df93b801ccc57ae 100644 (file)
--- a/src/decoder/major.csv
+++ b/src/decoder/major.csv
@@ -1,35 +1,35 @@
-opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe
-12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,0,NONE,0,0,addic
-13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,ZERO,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.
-14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addi
-15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,addis
-28,ALU,OP_AND,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.
-29,ALU,OP_AND,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.
-18,ALU,OP_B,NONE,CONST_LI,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,b
-16,ALU,OP_BC,SPR,CONST_BD,NONE,SPR,1,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bc
-11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,0,1,1,0,ONE,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi
-10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,0,1,1,0,ONE,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli
-34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz
-35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu
-42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,1,0,0,0,0,NONE,0,1,lha
-43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau
-40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz
-41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu
-32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz
-33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu
-7,ALU,OP_MUL_L64,RA,CONST_SI,NONE,RT,0,1,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli
-24,ALU,OP_OR,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,ori
-25,ALU,OP_OR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,oris
-20,ALU,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi
-21,ALU,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm
-23,ALU,OP_RLC,NONE,RB,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm
-38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stb
-39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbu
-44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth
-45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu
-36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw
-37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,ZERO,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu
-8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,1,0,ONE,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic
-2,ALU,OP_TDI,RA,CONST_SI,NONE,NONE,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi
-26,ALU,OP_XOR,NONE,CONST_UI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xori
-27,ALU,OP_XOR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris
+opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,
+12,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,0,1,NONE,0,0,0,0,0,0,NONE,0,0,addic
+13,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,0,0,0,1,NONE,0,0,0,0,0,0,ONE,0,0,addic.
+14,ALU,OP_ADD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,addi
+15,ALU,OP_ADD,RA_OR_ZERO,CONST_SI_HI,NONE,RT,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,addis
+28,ALU,OP_AND,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,ONE,0,0,andi.
+29,ALU,OP_AND,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,ONE,0,0,andis.
+18,ALU,OP_B,NONE,CONST_LI,NONE,NONE,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,1,0,b
+16,ALU,OP_BC,SPR,CONST_BD,NONE,SPR,1,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,1,0,bc
+11,ALU,OP_CMP,RA,CONST_SI,NONE,NONE,0,1,1,0,1,0,NONE,0,0,0,0,0,1,NONE,0,0,cmpi
+10,ALU,OP_CMP,RA,CONST_UI,NONE,NONE,0,1,1,0,1,0,NONE,0,0,0,0,0,0,NONE,0,0,cmpli
+34,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is1B,0,0,0,0,0,0,NONE,0,1,lbz
+35,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is1B,0,0,1,0,0,0,NONE,0,1,lbzu
+42,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,1,0,0,0,0,NONE,0,1,lha
+43,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,1,1,0,0,0,NONE,0,1,lhau
+40,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,0,0,0,0,0,NONE,0,1,lhz
+41,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is2B,0,0,1,0,0,0,NONE,0,1,lhzu
+32,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is4B,0,0,0,0,0,0,NONE,0,1,lwz
+33,LDST,OP_LOAD,RA_OR_ZERO,CONST_SI,NONE,RT,0,0,0,0,0,0,is4B,0,0,1,0,0,0,NONE,0,1,lwzu
+7,ALU,OP_MUL_L64,RA,CONST_SI,NONE,RT,0,1,0,0,0,0,NONE,0,0,0,0,0,1,NONE,0,0,mulli
+24,ALU,OP_OR,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,ori
+25,ALU,OP_OR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,oris
+20,ALU,OP_RLC,RA,CONST_SH32,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi
+21,ALU,OP_RLC,NONE,CONST_SH32,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm
+23,ALU,OP_RLC,NONE,RB,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm
+38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is1B,0,0,0,0,0,0,RC,0,1,stb
+39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is1B,0,0,1,0,0,0,RC,0,1,stbu
+44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is2B,0,0,0,0,0,0,NONE,0,1,sth
+45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu
+36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is4B,0,0,0,0,0,0,NONE,0,1,stw
+37,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,0,0,0,0,0,0,is4B,0,0,1,0,0,0,NONE,0,1,stwu
+8,ALU,OP_ADD,RA,CONST_SI,NONE,RT,0,0,1,0,1,1,NONE,0,0,0,0,0,0,NONE,0,0,subfic
+2,ALU,OP_TDI,RA,CONST_SI,NONE,NONE,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,1,tdi
+26,ALU,OP_XOR,NONE,CONST_UI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,xori
+27,ALU,OP_XOR,NONE,CONST_UI_HI,RS,RA,0,0,0,0,0,0,NONE,0,0,0,0,0,0,NONE,0,0,xoris

diff --git a/src/decoder/power_major_decoder.py b/src/decoder/power_major_decoder.py
index 0e0f1f22e5f9d1a92d8362f49cdb6b62c42b0ec4..b305cf594f172ba9210003f4844b611b348a0fbf 100644 (file)
--- a/src/decoder/power_major_decoder.py
+++ b/src/decoder/power_major_decoder.py
@@ -60,6 +60,15 @@ class OutSel(Enum):
     SPR = 3
 
 
+# names of the fields in major.csv that don't correspond to an enum
+single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out', 'cry in',
+                    'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
+                    'sgn', 'lk', 'sgl pipe']
+
+
+def get_signal_name(name):
+    return name.lower().replace(' ', '_')
+
 
 def get_csv(name):
     file_dir = os.path.dirname(os.path.realpath(__file__))
@@ -81,6 +90,10 @@ class PowerMajorDecoder(Elaboratable):
         self.in2_sel = Signal(In2Sel, reset_less=True)
         self.in3_sel = Signal(In3Sel, reset_less=True)
         self.out_sel = Signal(OutSel, reset_less=True)
+        for bit in single_bit_flags:
+            name = get_signal_name(bit)
+            setattr(self, name,
+                    Signal(reset_less=True, name=name))
 
     def elaborate(self, platform):
         m = Module()
@@ -96,13 +109,19 @@ class PowerMajorDecoder(Elaboratable):
                     comb += self.in2_sel.eq(In2Sel[row['in2']])
                     comb += self.in3_sel.eq(In3Sel[row['in3']])
                     comb += self.out_sel.eq(OutSel[row['out']])
+                    for bit in single_bit_flags:
+                        sig = getattr(self, get_signal_name(bit))
+                        comb += sig.eq(int(row[bit]))
         return m
 
     def ports(self):
-        return [self.opcode_in,
-                self.function_unit,
-                self.in1_sel,
-                self.in2_sel,
-                self.in3_sel,
-                self.out_sel,
-                self.internal_op]
+        regular =[self.opcode_in,
+                  self.function_unit,
+                  self.in1_sel,
+                  self.in2_sel,
+                  self.in3_sel,
+                  self.out_sel,
+                  self.internal_op]
+        single_bit_ports = [getattr(self, get_signal_name(x))
+                            for x in single_bit_flags]
+        return regular + single_bit_ports

diff --git a/src/decoder/test/test_power_major_decoder.py b/src/decoder/test/test_power_major_decoder.py
index bfffd7cffb313f5a2a7b8940c5a6e057a709b6f8..84c8d50e556ef77404ad818ddbd823f52eacb568 100644 (file)
--- a/src/decoder/test/test_power_major_decoder.py
+++ b/src/decoder/test/test_power_major_decoder.py
@@ -7,6 +7,7 @@ import unittest
 sys.path.append("../")
 from power_major_decoder import (PowerMajorDecoder, Function,
                                  In1Sel, In2Sel, In3Sel, OutSel,
+                                 single_bit_flags, get_signal_name,
                                  InternalOp, major_opcodes)
 
 
@@ -60,6 +61,12 @@ class DecoderTestCase(FHDLTestCase):
                 result = yield out_sel
                 expected = OutSel[row['out']].value
                 self.assertEqual(expected, result)
+
+                for bit in single_bit_flags:
+                    sig = getattr(dut, get_signal_name(bit))
+                    result = yield sig
+                    expected = int(row[bit])
+                    self.assertEqual(expected, result)
         sim.add_process(process)
         with sim.write_vcd("test.vcd", "test.gtkw", traces=[
                 opcode, function_unit, internal_op,