define CSR and register tables for SV

diff --git a/riscv/sv.h b/riscv/sv.h
new file mode 100644 (file)
index 0000000..ba40926
--- /dev/null
+++ b/riscv/sv.h
@@ -0,0 +1,48 @@
+// See LICENSE for license details.
+
+#ifndef _RISCV_SIMPLE_V_H
+#define _RISCV_SIMPLE_V_H
+
+// this table is for the CSRs (4? for RV32E, 16 for other types)
+// it's a CAM that's used to generate 2 tables (below)
+typedef struct {
+    unsigned int type   : 1; // 0=INT, 1=FP
+    unsigned int regkey : 5; // 5 bits
+    unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
+    unsigned int regidx : 6; // yes 6 bits
+    unsigned int isvec  : 1; // vector=1, scalar=0
+    unsigned int packed : 1; // Packed SIMD=1
+} sv_reg_csr_entry;
+
+// this is the "unpacked" table, generated from the CAM above
+// there are 2 of them: one for FP, one for INT regs.
+// one sv_reg_entry is required per FP *and* per INT reg.
+// note that regidx is 6 bits however we actually only have
+// 32 entries.  reason: the *actual* number of registers is doubled
+// in SV however the instruction is STILL ONLY 5 BITS.
+typedef struct {
+    unsigned int elwidth: 2; // 0=8-bit, 1=dflt, 2=dflt/2 3=dflt*2
+    unsigned int regidx : 6; // yes 6 bits.
+    unsigned int isvec  : 1; // vector=1, scalar=0
+    unsigned int packed : 1; // Packed SIMD=1
+    unsigned int active : 1; // enabled=1, disabled=0
+} sv_reg_entry;
+
+typedef struct {
+    unsigned int type  : 1; // 0=INT, 1=FP
+    unsigned int regkey: 5; // 5 bits: 
+    unsigned int zero  : 1; // zeroing=1, skipping=0
+    unsigned int inv   : 1; // inversion=1
+    unsigned int regidx: 6; // 6 bits
+    unsigned int active: 1; // enabled=1, disabled=0
+} sv_pred_csr_entry;
+
+typedef struct {
+    unsigned int regkey: 5; // 5 bits: 
+    unsigned int zero  : 1; // zeroing=1, skipping=0
+    unsigned int inv   : 1; // inversion=1
+    unsigned int regidx: 6; // 6 bits
+    unsigned int active: 1; // enabled=1, disabled=0
+} sv_pred_entry;
+
+#endif