put sv_mmu override class in place

diff --git a/dummy_rocc/dummy_rocc.cc b/dummy_rocc/dummy_rocc.cc
index 85ab7aa6946ed8b6d6813632632602108f5b88e4..7148aa8897d45aae34011373b3cc99ef3d7e0321 100644 (file)
--- a/dummy_rocc/dummy_rocc.cc
+++ b/dummy_rocc/dummy_rocc.cc
@@ -22,7 +22,11 @@ class dummy_rocc_t : public rocc_t
       case 1: // xd <- acc (the only real work is the return statement below)
         break;
       case 2: // acc[rs2] <- Mem[xs1]
-        acc[insn.rs2] = p->get_mmu()->load_uint64(xs1);
+        acc[insn.rs2] = p->get_mmu()->load_uint64(xs1)
+#ifdef NOT_SPIKE_SIMPLEV
+        .get_data()
+#endif
+;
         break;
       case 3: // acc[rs2] <- accX + xs1
         acc[insn.rs2] += xs1;

diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc
index 96de3c8ab234f59aa23cf079a16a9395f37acee4..4cf86693e662e568f9585ab150d7ddf8f0ecbded 100644 (file)
--- a/riscv/debug_module.cc
+++ b/riscv/debug_module.cc
@@ -274,13 +274,29 @@ void debug_module_t::sb_read()
   reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0];
   try {
     if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) {
-      sbdata[0] = sim->debug_mmu->load_uint8(address);
+      sbdata[0] = sim->debug_mmu->load_uint8(address)
+#ifdef NOTYET_SPIKE_SIMPLEV
+        .get_data()
+#endif
+;
     } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) {
-      sbdata[0] = sim->debug_mmu->load_uint16(address);
+      sbdata[0] = sim->debug_mmu->load_uint16(address)
+#ifdef NOTYET_SPIKE_SIMPLEV
+        .get_data()
+#endif
+;
     } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) {
-      sbdata[0] = sim->debug_mmu->load_uint32(address);
+      sbdata[0] = sim->debug_mmu->load_uint32(address)
+#ifdef NOTYET_SPIKE_SIMPLEV
+        .get_data()
+#endif
+;
     } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) {
-      uint64_t value = sim->debug_mmu->load_uint64(address);
+      uint64_t value = sim->debug_mmu->load_uint64(address)
+#ifdef NOTYET_SPIKE_SIMPLEV
+        .get_data()
+#endif
+;
       sbdata[0] = value;
       sbdata[1] = value >> 32;
     } else {

diff --git a/riscv/execute.cc b/riscv/execute.cc
index e639e90462cf9063404f5cfde99b712ad201b94f..eb8c79c758efe0d45a23df2f3fdbe9646d1f3ae0 100644 (file)
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -103,7 +103,11 @@ void processor_t::step(size_t n)
   while (n > 0) {
     size_t instret = 0;
     reg_t pc = state.pc;
+#ifdef SPIKE_SIMPLEV
+    sv_mmu_t* _mmu = mmu;
+#else
     mmu_t* _mmu = mmu;
+#endif
 
     #define advance_pc() \
      if (unlikely(invalid_pc(pc))) { \

diff --git a/riscv/interactive.cc b/riscv/interactive.cc
index b645c29e1c80a81b69a2bfea624deae41bd2eb40..28409637584446cfd9a24df94951981e6af7dff9 100644 (file)
--- a/riscv/interactive.cc
+++ b/riscv/interactive.cc
@@ -3,7 +3,11 @@
 #include "decode.h"
 #include "disasm.h"
 #include "sim.h"
+#ifdef SPIKE_SIMPLEV
+#include "sv_mmu.h"
+#else
 #include "mmu.h"
+#endif
 #include <sys/mman.h>
 #include <termios.h>
 #include <map>
@@ -264,7 +268,11 @@ reg_t sim_t::get_mem(const std::vector<std::string>& args)
     throw trap_interactive();
 
   std::string addr_str = args[0];
+#ifdef SPIKE_SIMPLEV
+  sv_mmu_t* mmu = debug_mmu;
+#else
   mmu_t* mmu = debug_mmu;
+#endif
   if(args.size() == 2)
   {
     processor_t *p = get_core(args[0]);
@@ -279,17 +287,33 @@ reg_t sim_t::get_mem(const std::vector<std::string>& args)
   switch(addr % 8)
   {
     case 0:
-      val = mmu->load_uint64(addr);
+      val = mmu->load_uint64(addr)
+#ifdef NOTYET_SPIKE_SIMPLEV
+            .get_data()
+#endif
+        ;
       break;
     case 4:
-      val = mmu->load_uint32(addr);
+      val = mmu->load_uint32(addr)
+#ifdef NOTYET_SPIKE_SIMPLEV
+            .get_data()
+#endif
+        ;
       break;
     case 2:
     case 6:
-      val = mmu->load_uint16(addr);
+      val = mmu->load_uint16(addr)
+#ifdef NOTYET_SPIKE_SIMPLEV
+            .get_data()
+#endif
+        ;
       break;
     default:
-      val = mmu->load_uint8(addr);
+      val = mmu->load_uint8(addr)
+#ifdef NOTYET_SPIKE_SIMPLEV
+            .get_data()
+#endif
+        ;
       break;
   }
   return val;
@@ -308,8 +332,13 @@ void sim_t::interactive_str(const std::string& cmd, const std::vector<std::strin
   reg_t addr = strtol(args[0].c_str(),NULL,16);
 
   char ch;
+#ifdef NOTYET_SPIKE_SIMPLEV
+  while((ch = debug_mmu->load_uint8(addr++).get_data()))
+    putchar(ch);
+#else
   while((ch = debug_mmu->load_uint8(addr++)))
     putchar(ch);
+#endif
 
   putchar('\n');
 }

diff --git a/riscv/mmu.h b/riscv/mmu.h
index 3f111a3729f4b0c46682ff091c5d9aa7e03bd4ec..0bcfb3c3cb71c8c209c83f69c52caad4babd0cac 100644 (file)
--- a/riscv/mmu.h
+++ b/riscv/mmu.h
@@ -393,4 +393,8 @@ inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t satp)
   }
 }
 
+#ifdef SPIKE_SIMPLEV
+#include "sv_mmu.h"
+#endif
+
 #endif

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 3586dc02126c907291bdb4e312e55d8209501f61..a7f6a923aba526f427e8852b92e3fb6dead9b6f0 100644 (file)
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -33,7 +33,11 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id,
   parse_isa_string(isa);
   register_base_instructions();
 
+#ifdef SPIKE_SIMPLEV
+  mmu = new sv_mmu_t(sim, this);
+#else
   mmu = new mmu_t(sim, this);
+#endif
 
   disassembler = new disassembler_t(max_xlen);
   if (ext)

diff --git a/riscv/processor.h b/riscv/processor.h
index 1ffdfab6f2512c96ba3a831a08fdc62191fa2251..41a1f22a6ae81cc70694289c31b9c4bb124ccc88 100644 (file)
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -17,6 +17,7 @@
 
 class processor_t;
 class mmu_t;
+class sv_mmu_t;
 typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t);
 class simif_t;
 class trap_t;
@@ -188,7 +189,11 @@ public:
   void step(size_t n); // run for n cycles
   void set_csr(int which, reg_t val);
   reg_t get_csr(int which);
+#ifdef SPIKE_SIMPLEV
+  sv_mmu_t* get_mmu() { return mmu; }
+#else
   mmu_t* get_mmu() { return mmu; }
+#endif
   state_t* get_state() { return &state; }
   unsigned get_xlen() { return xlen; }
   unsigned get_max_xlen() { return max_xlen; }
@@ -313,7 +318,11 @@ public:
 
 private:
   simif_t* sim;
+#ifdef SPIKE_SIMPLEV
+  sv_mmu_t* mmu;
+#else
   mmu_t* mmu; // main memory is always accessed via the mmu
+#endif
   extension_t* ext;
   disassembler_t* disassembler;
   state_t state;
@@ -339,6 +348,9 @@ private:
 
   void enter_debug_mode(uint8_t cause);
 
+#ifdef SPIKE_SIMPLEV
+  friend class sv_mmu_t;
+#endif
   friend class mmu_t;
   friend class clint_t;
   friend class extension_t;

diff --git a/riscv/sim.cc b/riscv/sim.cc
index 44223a7d90b59772faffe36af4967ffbf2b27f3e..de57edfdbc2150e68e04724a47ca1217a8847c0a 100644 (file)
--- a/riscv/sim.cc
+++ b/riscv/sim.cc
@@ -41,7 +41,11 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc,
 
   debug_module.add_device(&bus);
 
+#ifdef SPIKE_SIMPLEV
+  debug_mmu = new sv_mmu_t(this, NULL);
+#else
   debug_mmu = new mmu_t(this, NULL);
+#endif
 
   if (hartids.size() == 0) {
     for (size_t i = 0; i < procs.size(); i++) {

diff --git a/riscv/sim.h b/riscv/sim.h
index b847bdb67a8e610a63a612ccbcb6bddfaccc69f0..2a5df26605cc45238efc4eb634a05aa63b295fe7 100644 (file)
--- a/riscv/sim.h
+++ b/riscv/sim.h
@@ -13,7 +13,11 @@
 #include <string>
 #include <memory>
 
+#ifdef SPIKE_SIMPLEV
+class sv_mmu_t;
+#else
 class mmu_t;
+#endif
 class remote_bitbang_t;
 
 // this class encapsulates the processors and memory in a RISC-V machine.
@@ -47,7 +51,11 @@ public:
 
 private:
   std::vector<std::pair<reg_t, mem_t*>> mems;
+#ifdef SPIKE_SIMPLEV
+  sv_mmu_t* debug_mmu;
+#else
   mmu_t* debug_mmu;  // debug port into main memory
+#endif
   std::vector<processor_t*> procs;
   reg_t start_pc;
   std::string dts;