self.comb = comb
self.sync = sync
- self.ra_en = Signal(reset=1)
- self.rb_en = Signal(reset=1)
- self.wen = Signal(name="register_wen")
+ self.ra_en = Signal(reset=1, name="regfile_ra_en") # TODO: ondemand en
+ self.rs1 = Signal(32, name="regfile_rs1")
+ self.rs_a = Signal(5, name="regfile_rs_a")
- self.rs1 = Signal(32, name="register_rs1")
- self.rs2 = Signal(32, name="register_rs2")
- self.wval = Signal(32, name="register_wval")
+ self.rb_en = Signal(reset=1, name="regfile_rb_en") # TODO: ondemand en
+ self.rs2 = Signal(32, name="regfile_rs2")
+ self.rs_b = Signal(5, name="regfile_rs_b")
- self.rs_a = Signal(5, name="register_rs_a")
- self.rs_b = Signal(5, name="register_rs_b")
- self.rd = Signal(32, name="register_rd")
+ self.w_en = Signal(name="regfile_w_en")
+ self.wval = Signal(32, name="regfile_wval")
+ self.rd = Signal(32, name="regfile_rd")
class CPU(Module):
"""
def write_register(self, rd, val):
return [self.regs.rd.eq(rd),
self.regs.wval.eq(val),
- self.regs.wen.eq(1)
+ self.regs.w_en.eq(1)
]
def handle_valid(self, mtvec, mip, minfo, misa, csr, mi, m, mstatus, mie,
i = If((ft.action == FA.ack_trap) | (ft.action == FA.noerror_trap),
[self.handle_trap(m, mstatus, ft, dc,
load_store_misaligned),
- self.regs.wen.eq(0) # no writing to registers
+ self.regs.w_en.eq(0) # no writing to registers
]
)
i = i.Elif((dc.act & (DA.fence | DA.fence_i |
DA.store | DA.branch)) != 0,
# do nothing
- self.regs.wen.eq(0) # no writing to registers
+ self.regs.w_en.eq(0) # no writing to registers
)
return i
rf = Instance("RegFile", name="regfile",
i_ra_en = self.regs.ra_en,
i_rb_en = self.regs.rb_en,
- i_w_en = self.regs.wen,
+ i_w_en = self.regs.w_en,
o_read_a = self.regs.rs1,
o_read_b = self.regs.rs2,
i_writeval = self.regs.wval,