reduce number of d-cache lines in microwatt fpga mode
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)

No differences found