reduce number of d-cache lines in microwatt fpga mode
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 18 Feb 2022 19:42:44 +0000 (19:42 +0000)
commitfdd55337edc5856dc5ae0c35cd6ad28151bfc441
treefdc5e71cf0d566b284197fdb29136b7f5f3dcc97
parent1d3441ee494729433c8f5f18924c0f60f68374af
reduce number of d-cache lines in microwatt fpga mode
src/soc/experiment/dcache.py