reduce number of d-cache lines in microwatt fpga mode

[soc.git] / src / soc / experiment / dcache.py

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index 04c222faefea4d19d21386602fe135d7fc5e4c91..3b67b7cf0721f2508a8ea530b0b43f91cd6dde52 100644 (file)
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -745,7 +745,7 @@ class DCache(Elaboratable, DCacheConfig):
 
         if self.microwatt_compat:
             # reduce way sizes and num lines
-            super().__init__(NUM_LINES = 16,
+            super().__init__(NUM_LINES = 8,
                               NUM_WAYS = 1,
                               TLB_NUM_WAYS = 1,
                               TLB_SET_SIZE=16) # XXX needs device-tree entry