git.libre-soc.org Git - litex.git/history - litex/soc/cores/cpu/zynq7000/core.py

2020-08-06	Florent Kermarrec	cores/cpu/zynq7000: simplify using new loose parameter...	blob \| commitdiff \| raw
2020-08-06	enjoy-digital	Merge pull request #624 from trabucayre/emio_zynq	blob \| commitdiff \| raw \| diff to current
2020-08-06	Gwenhael Goavec...	soc/cores/cpu/zynq7000: add enet0, enet0_mdio, sdio...	blob \| commitdiff \| raw \| diff to current
2020-08-05	enjoy-digital	Merge pull request #622 from antmicro/fix_connectors	blob \| commitdiff \| raw \| diff to current
2020-08-04	enjoy-digital	Merge pull request #619 from antmicro/jboc/sim-clocker	blob \| commitdiff \| raw \| diff to current
2020-08-03	enjoy-digital	Merge pull request #615 from pepijndevos/openfpgaloader	blob \| commitdiff \| raw \| diff to current
2020-07-30	Florent Kermarrec	cpu/zynq7000: set csr map to 0x00000000.	blob \| commitdiff \| raw \| diff to current
2020-07-24	enjoy-digital	Merge pull request #604 from antmicro/jboc/axi-lite	blob \| commitdiff \| raw \| diff to current
2020-07-23	Florent Kermarrec	core/cpu: integrate Zynq as a classical CPU (Zynq7000...	blob \| commitdiff \| raw \| diff to current