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remove "sv." and replace with "sv" in all SVP64Asm
[soc.git]
/
src
/
soc
/
fu
/
alu
/
test
/
svp64_cases.py
2021-03-14
Luke Kenneth Casso...
remove "sv." and replace with "sv" in all SVP64Asm
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2021-03-11
Cesar Strauss
Bring a few test cases from test_caller_64.py
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2021-03-11
Cesar Strauss
Test case for two successive SV instructions
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2021-03-09
Cesar Strauss
Enable VL==0 vector instruction skip test case
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2021-03-08
Luke Kenneth Casso...
correct comments in sv.add rc=1
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2021-03-07
Luke Kenneth Casso...
add Rc=1 SVP64 unit test to svp64_cases.py
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2021-03-06
Cesar Strauss
Enable the Simple-V loop test case
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2021-02-26
Cesar Strauss
Add a vector case with VL == 0
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2021-02-17
Cesar Strauss
Add a case for checking the EXTRA field and register...
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2021-02-15
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-02-13
Cesar Strauss
Skip vector test case, and add a scalar case
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2021-02-13
Cesar Strauss
Fix imports and whitespace
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2021-02-13
Luke Kenneth Casso...
add SVP64 TestIssuer separate unit test
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