Add a HDL test case, where we start at the middle of the VL loop
[soc.git] / src / soc / fu / alu / test / svp64_cases.py
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of...
2021-04-03 Cesar StraussFix typo
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero
2021-04-03 Cesar StraussAdd a test case for integer single predication
2021-04-03 Cesar StraussEnable remaining disabled test cases
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc
2021-03-30 Cesar StraussEnable VCOMPRESS test case
2021-03-30 Cesar StraussAdd new twin predication case
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax
2021-03-22 Cesar StraussAdd test cases for integer VCOMPRESS and VEXPAND
2021-03-21 Luke Kenneth Casso... adjust syntax of SVP64 predicate test cas
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly
2021-03-21 Cesar StraussAdd predication test case, initially disabled
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm
2021-03-11 Cesar StraussBring a few test cases from test_caller_64.py
2021-03-11 Cesar StraussTest case for two successive SV instructions
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case
2021-03-08 Luke Kenneth Casso... correct comments in sv.add rc=1
2021-03-07 Luke Kenneth Casso... add Rc=1 SVP64 unit test to svp64_cases.py
2021-03-06 Cesar StraussEnable the Simple-V loop test case
2021-02-26 Cesar StraussAdd a vector case with VL == 0
2021-02-17 Cesar StraussAdd a case for checking the EXTRA field and register...
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-13 Cesar StraussSkip vector test case, and add a scalar case
2021-02-13 Cesar StraussFix imports and whitespace
2021-02-13 Luke Kenneth Casso... add SVP64 TestIssuer separate unit test